Lesson 13/1776%
MODULE 13

Testing and Validation

Proving the barrier and the transfer function: Hi-Pot test procedures and their pitfalls, isolation resistance measurement, bench CTR characterization, EMC validation of isolated interfaces, thermal testing, and economical production test strategies.

Learning Objectives

After completing this module, you will be able to:

Specify and run Hi-Pot tests safely and correctly
Measure isolation resistance and interpret results
Characterize CTR on the bench across conditions
Validate EMC performance of isolated interfaces
Design production test coverage for isolation circuits
Where this fits. Module 12 showed how isolated interfaces fail. This module shows how to prove they won’t: type tests that prove the design with margin, bench characterisation of the transfer function, EMC validation, and production tests that prove every unit was built correctly without damaging it. It uses the parameters from Module 6, the margins from Module 9 and the failure modes from Module 12. The standards behind the test levels are covered in Module 16.
Illustrations and animations are original teaching drawings, not to scale. Values marked representative are typical of common parts; always confirm against the current datasheet or standard you design to.

A coupler datasheet proves the component. It says nothing about your creepage, your flux residue, your Y-capacitors or the 2 kV burst that couples in through a 20 m sensor cable. Validation is layered: each level proves something the level below cannot, and the cost per test rises as you go up.

Pyramid with four levels: component qualification at the base, then board or sub-assembly, then system, then production at the top, each with example tests
Figure 1. The isolation test pyramid. The top level runs on every unit; the lower levels run on samples.
Type (design) testRoutine (production) test
PurposeProve the design meets the standard with marginProve each unit was built correctly
SamplesA few units, often pre-conditioned (damp heat, thermal cycling)Every unit (100 %)
Hi-Pot exampleFull level for ~60 sSame level for ~1 s (or as the standard allows)
Destructive?May be; the units are scrapped afterwardsMust not degrade the unit that ships
ExamplesHi-Pot, PD, EMC, thermal, touch current, CMTI, life testHi-Pot, functional I/O, ICT, sample RIO
Design trap — treating the vendor’s isolation test as your isolation test. The vendor tested the coupler in air, with clean pins. Your board adds creepage over solder mask, contamination, conformal coating defects, via placement and other parts bridging the barrier. Only a board- or system-level test proves those.
Pro tip Write the test plan while you design, not after the prototype arrives. Every requirement in the specification (working voltage, insulation class, CMTI, CTR at end of life) should map to at least one test with a numeric pass criterion. Section 11 gives a template.

A Hi-Pot test applies a voltage far above the working voltage across the insulation for a defined time and checks that nothing breaks down. It does not measure lifetime or partial discharge: a barrier can pass Hi-Pot and still age from PD at working voltage (that is what the PD test in Section 4 is for).

AC test

Stresses the insulation like mains does, including PD at peaks. Capacitive current flows through Y-caps and the barrier capacitance, so the tester sees current even with perfect insulation.

DC test

No capacitive current once charged, so leakage is easy to see and Y-caps don’t trip it. The equivalent DC voltage is the AC peak. The DUT stores charge and must be discharged afterwards.

Ramp

Raise the voltage gradually (seconds, not instantly) so the charging current and any overshoot don’t cause false trips or overstress.

Dwell

The time at full voltage: typically 60 s for type tests and about 1 s for routine tests. Take the actual times from your standard.

Trip current

The tester removes the voltage when the current exceeds this. Set it above the normal (capacitive plus leakage) current but low enough to catch a breakdown.

Arc detection

Some testers flag short, high-frequency current bursts (flashover or corona) that never reach the trip level.

VDC,eq = √2 × VAC,rms ≈ 1.414 × VAC,rms     IC = 2π f C VAC,rms
  • VAC,rms: specified AC test voltage (Vrms); VDC,eq: equivalent DC test voltage (V)
  • f: test frequency (50 or 60 Hz); C: total capacitance across the barrier (F): Y-caps plus the coupler’s CIO (≈ 0.5–1 pF each)
  • IC: capacitive current the tester sees with perfect insulation (Arms)
Animation of two Hi-Pot runs: a good unit whose current follows the capacitive current through ramp, dwell and ramp-down, and a contaminated unit that breaks down during the ramp and trips the tester
Figure 2 (animation). Ramp, dwell and ramp-down, first on a good unit and then on a unit that breaks down.
Worked example — AC or DC for a board with Y-caps?

A 230 V mains SMPS has 2 × 2.2 nF Y-caps in parallel across the barrier (4.4 nF). The end-product standard calls for a representative 3000 Vrms between primary and SELV.

  1. Capacitive current at 50 Hz: IC = 2π × 50 × 4.4 nF × 3000 V = 4.1 mA.
  2. A typical 5 mA trip gives only 0.9 mA of margin; at 60 Hz (4.98 mA) it trips a good board.
  3. DC alternative (if the standard allows it): 1.414 × 3000 = 4243 V DC. Once charged, the current is only leakage (nA to µA), so a trip of 0.1–0.5 mA is meaningful.
  4. Stored energy after the DC test: ½ C V2 = ½ × 4.4 nF × 42432 ≈ 40 mJ. That is a painful shock, so discharge before touching.
Design trap — raising the AC trip limit until the test passes. A 20 mA trip limit on a board with 4 mA of capacitive current cannot see a 10 mA leakage fault. Fix the method (DC, or test before fitting the Y-caps) rather than blinding the tester.

Getting the connections right matters as much as the voltage. Every pin on each side is shorted together so the full voltage appears only across the insulation under test, never across a single junction inside the coupler or across another part.

Hi-Pot test set-up: tester with HV and return terminals inside an interlocked enclosure; the DUT board has all primary-side pins shorted to HV and all secondary-side pins shorted to return, with a Y-capacitor across the isolation barrier
Figure 3. Correct Hi-Pot connection of an isolated board.

Procedure

Routine Hi-Pot on an isolated board
  1. Guard: interlocked fixture or enclosure, two-hand start or light curtain, HV warning lamp. Only trained operators.
  2. Short all primary-side nets to HV and all secondary-side nets (and SELV connectors) to return. Test primary–PE separately where it is a different insulation class.
  3. Verify the tester with a known-good and a known-bad reference (a “fail” resistor) at the start of each shift.
  4. Ramp to the test voltage, dwell, ramp down. Record voltage, time, maximum current and pass/fail with the serial number.
  5. Discharge (automatic in most DC testers) and confirm 0 V before releasing the fixture.
Stored charge

After a DC test, Y-caps and bulk caps can hold kV. Use the tester’s discharge function and a grounding stick in the lab.

Repeated tests

Each full-level test stresses the barrier. Standards and vendors generally recommend a reduced level (often around 80 %) for retests after rework.

Surge suppressors

MOVs, TVS diodes and spark gaps from line to PE will conduct during a Hi-Pot test. They are usually disconnected for the test, as the standard allows.

Wrong sides shorted

Forgetting one secondary net leaves it floating: it charges through stray capacitance and may arc to a neighbour, a false fail or real damage.

Interactive: Hi-Pot Test Planner

Pick the insulation class, working voltage and test type. The planner suggests a representative test voltage (a simplified rule: basic ≈ max(1500 V, 2VW + 1000 V)rms, reinforced = 2 × basic), timing and trip setting, then animates the run. Always take the actual values from your end-product standard.

Test voltage–
Timing–
Expected current–
Suggested trip setting–
–

The simplified rule reproduces the familiar 1.5 kVrms basic / 3 kVrms reinforced levels for 230 V mains, but modern standards (IEC 62368-1, IEC 61010-1, IEC 60601-1) derive test voltages from tables of peak working voltage, transient overvoltage and insulation class. Use their tables. See Module 16.

Partial discharge (PD) is what slowly kills a barrier at working voltage (Module 12, Section 7). A Hi-Pot test cannot see it; a PD test can. The measurement follows IEC 60270: a coupling capacitor and measuring impedance detect the tiny charge pulses, reported as apparent charge in picocoulombs (pC).

Inception voltage

The voltage at which PD starts as you raise the voltage. It must be comfortably above the peak working voltage.

Extinction voltage

The voltage at which PD stops as you lower it again. It is usually lower than inception, which is why the test goes down to the measurement level after a higher stress.

Threshold

Optocoupler datasheets typically quote a PD limit of about 5 pC at the test level.

Who tests

For couplers certified to IEC 60747-5-5, the vendor PD-tests 100 % of parts. Board-level PD testing needs a shielded set-up and is mostly done for high-voltage designs (drives, PV, medical).

Two voltage-time profiles: method a applies V_IOTM for about 60 seconds then reduces to about 1.6 times V_IORM for a 10-second PD measurement; method b1 applies about 1.875 times V_IORM for about 1 second on every part
Figure 4. PD test profiles as they appear in IEC 60747-5-5 coupler datasheets (representative).
Vpd(m) ≈ F × VIORM,   qpd < 5 pC
  • VIORM: maximum repetitive peak working voltage the barrier is certified for (Vpeak)
  • F: test factor; about 1.875 for the 100 % routine test (method b1, 1 s) and about 1.6 for the sample test after environmental stress (method a, 10 s), as commonly listed on datasheets
  • qpd: apparent charge (pC)
Worked example — reading the PD figures

A gate-drive coupler lists VIORM = 891 Vpeak.

  1. Routine (every part): 1.875 × 891 ≈ 1671 Vpeak for 1 s, PD < 5 pC.
  2. Sample (after stress): 1.6 × 891 ≈ 1426 Vpeak for 10 s, PD < 5 pC.
  3. Your peak working voltage must not exceed 891 Vpeak, including DC-link ripple and switching overshoot (Module 9).
Verify Test factors, times and the PD limit depend on the insulation class and the edition of IEC 60747-5-5. Read them from the part’s certificate, not from this page.

An insulation-resistance test (“megger” test) applies a moderate DC voltage, typically 500 V or 1000 V DC, and reports resistance. It is non-destructive, gives a number you can trend, and is very sensitive to contamination and moisture. It complements Hi-Pot: Hi-Pot proves withstand; IR shows surface and bulk quality.

Three charts: apparent resistance rising over ten minutes as absorption current decays, with a higher polarisation index for clean insulation; surface resistance falling with humidity, much faster for a flux-contaminated board; and R_IO halving about every 10 degrees C
Figure 5. Why an IR reading needs time, humidity and temperature recorded alongside it (representative curves).
Read at a fixed time

The reading rises for minutes as absorption current decays. Use 60 s unless your procedure says otherwise. The ratio R10 min/R1 min (polarisation index) above about 2 indicates dry, clean insulation.

Use the guard terminal

To measure the coupler bulk and not the board surface (or the reverse), connect the megger’s guard to a ring around one side to divert surface current.

Humidity dominates

Clean boards lose perhaps one decade from 20 % to 90 % RH; flux-contaminated ones lose several. A low reading at high RH that recovers after drying means a surface problem.

Temperature

Bulk resistance roughly halves for every ~10 °C rise (representative). Compare readings only at similar temperatures, or correct them.

Interactive: Insulation-Resistance and Leakage Calculator

Parallel leakage paths across the barrier (couplers, board surface, bleeders) set the insulation resistance; the barrier capacitance sets the AC leakage. Limits shown are representative — verify with IEC 62368-1 / IEC 61010-1 / IEC 60601-1 as applicable.

Total insulation resistance–
Megger current–
Resistive leakage at VW–
Capacitive leakage at VW–
Total leakage (vector sum)–
–

Worked example — why a medical design fails on Y-caps, not couplers
  1. 4 couplers at 50 GΩ each in parallel = 12.5 GΩ. At 230 V: 18 nA resistive leakage, which is negligible.
  2. A 2.2 nF Y-cap at 230 V, 50 Hz: 2π × 50 × 2.2 nF × 230 = 159 µA.
  3. That exceeds a representative 10 µA CF limit sixteen-fold. The fix is to remove the Y-cap across the patient barrier (and solve EMI another way), not to change the coupler.

Datasheet curves are typical. Before committing to a design you should characterise a few parts yourself: it catches wrong ranks and counterfeit parts, and gives you data at your operating point, which is rarely the datasheet’s 5 mA / 5 V test condition.

Bench set-up: a source-measure unit forcing I_F into the LED, a second SMU forcing V_CE = 5 V and measuring I_C, the DUT inside a thermal chamber with a thermocouple on the package
Figure 6. Two-SMU CTR bench. A current source plus a voltage source and ammeter works too.
CTR = (IC / IF) × 100 %   at stated VCE and TA
  • IC: collector current measured with VCE held constant (mA)
  • IF: forced LED current (mA)
  • VCE: collector–emitter voltage, typically 5 V (V); TA: chamber temperature (°C)
Animation of a CTR characterisation: points are added as I_F is stepped from 0.5 to 30 mA at minus 40, 25 and 85 degrees C, building three curves
Figure 7 (animation). Building the CTR map: sweep IF at each temperature.

Interactive: CTR Measurement Lab

A virtual bench with a PC817-class teaching model (typical part, ±2 % measurement scatter). Set IF and temperature, press Measure point to log readings, and build your own CTR curves. Try the DC option at 30 mA to see self-heating.

Reading: IC at VCE = 5 V–
VF–
CTR–
LED junction temperature–
–

0 points logged

TAIF (mA)IC (mA)CTR (%)
Worked example — incoming check of a CTR rank

You receive PC817C parts (rank C: 200–400 % at IF = 5 mA, VCE = 5 V, 25 °C). Five samples read IC = 11.8, 13.1, 12.4, 9.1 and 12.9 mA at 5 mA.

  1. CTR = 236, 262, 248, 182, 258 %.
  2. One part is below the rank’s 200 % floor. Re-measure (check VCE, temperature, pulse timing); if it is confirmed, quarantine the lot and ask the distributor for traceability.
  3. A consistent shift of all samples by a fixed factor often points to a set-up error (wrong VCE, self-heating). A single outlier points to the parts.
Design trap — characterising at 25 °C only. CTR falls at both ends of the temperature range for many phototransistor couplers (Module 6). A design that works on the bench can fail at −25 °C in a cabinet in winter. Always include the temperature extremes of your specification.

Timing and common-mode tests validate the dynamic side of the interface. Both are very sensitive to the fixture: a 10 cm ground lead on a scope probe can add more ringing than the part produces.

ParameterHow to measurePitfalls
tPHL, tPLH50 % input to 50 % output (or the thresholds in the datasheet test circuit), at the datasheet RL and CL and at your ownProbe capacitance adds to CL; use ≤ 10 pF active or low-C passive probes
PWD (|tPHL − tPLH|)Same set-up; measure both edges, over temperature and supplyPWD changes with LED current and temperature; check the worst corner
tr, tf10–90 % of the output swingPhototransistor fall/rise depend on RL (Miller effect, Module 4)
CMTICommon-mode pulse between the two grounds; output monitored for a glitchScope must be referenced to the output side only; measure dV/dt at the DUT pins
CMTI bench set-up: a common-mode pulse generator connected between the input ground and the output ground of the DUT, the input held high or low, and a scope referenced to the output ground watching for glitches
Figure 8. CMTI test: the pulse generator drives the whole input side relative to the output side.
dV/dt = 0.8 × VCM / t10–90
  • VCM: common-mode pulse amplitude (V)
  • t10–90: 10–90 % rise (or fall) time of the pulse measured at the DUT (s)
  • Result usually quoted in kV/µs
Worked example — is the test hard enough?

Your SiC inverter switches 800 V in 20 ns (10–90 %), which is 0.8 × 800 / 20 ns = 32 kV/µs at the gate-drive barrier. The lab pulse generator gives 1.2 kV with a 40 ns rise.

  1. Generator dV/dt = 0.8 × 1200 / 40 ns = 24 kV/µs, which is less than the application.
  2. The test cannot prove the requirement. Use a faster generator or a smaller fixture capacitance, or validate in the real inverter with a differential probe and output-glitch monitoring.
  3. Aim for at least 2× the application dV/dt in the test, which suits a coupler rated ≥ 50 kV/µs (e.g. ACPL-332J / TLP5214-class; check the datasheet).
Pro tip Test both states (output HIGH and output LOW) and both edge polarities. Many couplers glitch in only one combination, which is usually the one you didn’t test.

EMC testing is where isolated interfaces are exposed to real-world abuse. The barrier capacitance (CIO plus layout) gives fast common-mode transients a path across; long cables deliver them. The basic standards define the waveforms; the generic or product standards (e.g. IEC 61000-6-1 / -6-2, or a product-family standard) set the levels and performance criteria.

Four panels: ESD contact-discharge current waveform with a sub-nanosecond first peak; EFT 5/50 ns pulse with burst timing inset; surge combination wave with 1.2/50 microsecond voltage and 8/20 microsecond current; and a text panel explaining how each test couples into an isolated interface
Figure 9. The three transient immunity waveforms and how they reach an optocoupler (shapes approximated for teaching).
Basic standardTest levels 1 / 2 / 3 / 4 (open-circuit)Coupling
IEC 61000-4-2 ESDcontact 2 / 4 / 6 / 8 kV; air 2 / 4 / 8 / 15 kVDirect to touchable points; indirect via coupling planes
IEC 61000-4-4 EFT/burstpower 0.5 / 1 / 2 / 4 kV; signal 0.25 / 0.5 / 1 / 2 kVCDN on power; capacitive clamp on I/O cables
IEC 61000-4-5 surge0.5 / 1 / 2 / 4 kVLine–line (2 Ω) and line–earth (12 Ω) via CDN

Level summary for orientation; the standards define tolerances, set-ups and additional levels. Check the edition you test to.

Criterion A

Normal performance within specification during and after the test.

Criterion B

Temporary degradation or loss of function during the test that recovers by itself afterwards; no change of stored data or operating mode.

Criterion C

Temporary loss of function that needs operator intervention or a system reset.

Criterion D

Loss of function that is not recoverable (damage). Never acceptable.

Interactive: EMC Test-Level Reference and Pass-Criteria Explainer

Levels shown are representative of the generic immunity standards; product standards may be stricter. Verify against the current edition you test to.

TestPort / applies toRepresentative levelCriterion

Pass-criteria explainer

Observed behaviour–
–

Design trap — testing the board on the bench instead of the system. Cable routing, enclosure bonding, the PE connection and the power supply all change the result. An ESD pass on the bench says little about the finished product.
Pro tip Instrument the isolated interface during EMC testing: count UART framing errors, log PLC input transitions, or use a spare channel that should never change. “Criterion A” claimed without monitoring is a guess.

Optocoupler ageing depends on LED junction temperature (Module 9), so validate the temperature in the real product: enclosure closed, maximum ambient, worst-case load, after thermal equilibrium (typically 1–2 h for a closed enclosure).

An optocoupler on a PCB with a fine-gauge thermocouple bonded to the top centre and an IR camera aimed at a patch of matt-black tape; equation T_J approximately equals T_top plus psi_JT times power
Figure 10. Measuring package temperature and estimating TJ.
TJ ≈ Ttop + ψJT × P,   P = VF IF + VCE IC
  • Ttop: measured package top temperature (°C)
  • ψJT: junction-to-top characterisation parameter (°C/W; representative 20–50 °C/W for small packages, often not published; see JEDEC JESD51)
  • P: total dissipation (W): LED plus output transistor

Interactive: Junction-Temperature Estimate

Enter your measurement. For these low-power parts TJ is only slightly above Ttop; the real danger is a hot neighbour raising the local ambient.

Dissipation P–
Estimated TJ–
Margin to limit–
–

Thermocouple choice

Fine gauge (36–40 AWG), bead bonded with thermally conductive epoxy. A heavy thermocouple heat-sinks the package and reads low.

IR camera

Put matt-black tape or paint (ε ≈ 0.95) on the part, or calibrate emissivity against a thermocouple.

VF as a thermometer

Calibrate VF at a small pulsed current against chamber temperature (≈ −1.5 to −2 mV/°C), then read it in-circuit to get the LED junction temperature directly.

Report

Log TA next to the part, the enclosure and airflow state, load, and time to equilibrium.

Production testing must catch assembly defects on every unit, quickly and without degrading the product. Design for test at schematic stage: test points on both sides of the barrier, a way to drive each isolated input, and a way to read each isolated output.

Production test flow of AOI, ICT, Hi-Pot, functional and end-of-line sample stations, above a matrix of seven typical faults showing which stations reliably or partly detect each
Figure 11. Production stations and the faults each one catches (illustrative).
TestCoverageTypical timeNotes
AOI / X-rayPlacement, polarity, solder bridges, lead-frame bridges under the partsecondsCatch a rotated coupler before Hi-Pot
ICTComponent values, opens/shorts; LED VF via test padssecondsNeeds pads on both sides; the barrier breaks the fixture’s ground reference
Hi-Pot (routine)Barrier breakdown, bridges across creepage, contamination at high field1–3 sMandatory in many safety standards for mains-connected equipment
FunctionalTransfer at the limit: drive the input at minimum IF, check the output switchessecondsThe only test that catches a weak CTR on the board
Sample IR / burn-inProcess drift, contamination trend, early-life failuresminutes–hoursSampling detects trends, not individual bad units
Worked example — a functional test that screens CTR

A PLC input must switch at 15 V with an end-of-life CTR of at least 60 %. The production test drives the input at the threshold condition, not at 24 V.

  1. Apply 15 V (not 24 V) so IF is at its design minimum.
  2. Check the output logic level is valid with the maximum pull-up resistor tolerance simulated (or accept a guard-banded limit on the output voltage).
  3. A unit with a low-rank or damaged coupler fails here, though it would pass a 24 V go/no-go test.

Interactive: Sampling vs 100 % Test

P(detect) = 1 − (1 − p)n. Small defect rates need very large samples, which is why safety tests run on every unit.

Probability the sample contains ≥ 1 defect–
Defective units shipped from the untested rest–
–

Pull everything together in a design-verification (DVT) matrix: one row per requirement, one test per row, a numeric pass criterion, a sample size and a link to evidence. It becomes the core of your certification file (Module 16).

RequirementTestSamplesPass criterion (example)Evidence
Reinforced insulation, 230 V mainsHi-Pot type test after humidity conditioning3 boardsNo breakdown at the standard’s level for 60 sTest report + photos of set-up
Barrier working voltageReview VIORM, creepage/clearance measurementDesign + 1 boardVIORM ≥ peak VW; creepage ≥ requiredCertificate + measurement record
Leakage / touch currentMeasure at 1.1 × mains, 60 Hz3 units< limit of end-product standardReport
CTR at end of lifeBench CTR at Tmin/Tmax; functional at threshold10 parts / 3 boardsMargin ≥ ageing factor from Module 9Data file + plots
Timing / PWDScope measurement over temperature5 boardsPWD < budget; tP < specScope captures
CMTICommon-mode pulse test / in-system3 boardsNo glitch at ≥ 2× application dV/dtCaptures
EMC immunityESD, EFT, surge, conducted RF per product standard1–2 systemsCriterion A/B as requiredAccredited lab report
ThermalThermocouple at max TA, closed enclosure2 systemsTJ ≤ derated limit − 10 °CReport
Pro tip Re-run the Hi-Pot and IR tests after environmental conditioning (damp heat, thermal cycling). Many contamination and delamination problems only appear after stress, and that is also what the standards’ type-test sequences do.
Layered proof

Component data, board type tests, system EMC/thermal and production tests each prove something different.

Type vs routine

Type tests prove the design with margin; routine tests prove each unit without damaging it.

AC vs DC Hi-Pot

DC equivalent = 1.414 × ACrms. AC current includes Y-cap charging; DC hides it but stores energy.

Connections

Short all pins on each side; test each barrier separately; discharge afterwards.

Hi-Pot ≠ PD

Withstand does not prove freedom from partial discharge; the vendor’s PD test covers the coupler.

IR needs context

Record voltage, time, temperature and RH. Humidity collapses dirty surfaces.

Characterise CTR

Pulsed, at your operating point and at temperature extremes.

Instrument EMC tests

Monitor the isolated channel to claim criterion A or B honestly.

Test at threshold

Functional production tests at the minimum drive condition screen weak couplers.

Design checklist

Tick items as you review a design. Your ticks are saved in this browser only; use your browser’s print function for a sign-off copy.

Four parts: multiple choice, true/false, a matching exercise and engineering scenarios. Score 80 % on the multiple choice to pass the module.

Part A — Multiple Choice

Question 1 of 10  •  Score: 0/10

Part B — True or False

Score: 0/8

Part C — Match the Term to Its Meaning

Drag each term onto its definition, or click a term and then click a definition.

Placed: 0/6

Part D — Engineering Scenarios

Scenario 1 — The production line that trips at 60 Hz
A product passes routine Hi-Pot (3 kVrms, 5 mA trip) in Europe. The same product, tested at the US factory at 60 Hz, fails about 30 % of units. There is 4.4 nF of Y-capacitance across the barrier.
Analysis. IC = 2π × 60 × 4.4 nF × 3000 = 4.98 mA, right at the 5 mA trip; Y-cap tolerance (±20 %) decides pass or fail. At 50 Hz it was 4.15 mA. Fix: use the equivalent DC test (4243 V DC, trip about 0.5 mA) if the standard allows, or raise the AC trip with justification (for example 8 mA) and verify with a reference fault. Don’t just raise the trip until it passes.
Scenario 2 — The megger that disagreed
An IR test at 500 V DC reads 400 MΩ in the morning (RH 85 %, unconditioned lab) and 60 GΩ in the afternoon after the air conditioning starts (RH 45 %). The spec requires ≥ 1 GΩ.
Analysis. A 150× swing with humidity is a surface-contamination signature (clean boards typically change by less than one decade). Inspect for flux residue in the creepage gap; clean, bake and retest at a controlled RH. Add RH and temperature to the test procedure and a cleaning/coating step to production. Also rerun the Hi-Pot after damp-heat conditioning: the board passed a dry test but may track in the field.
Scenario 3 — The EMC glitch
During a ±2 kV EFT test on a 24 V PLC input cable, a 6N137-based input produces 2–3 false pulses per burst; the PLC counts them. The product standard requires criterion B for this port.
Analysis. Counted false pulses corrupt data, so this does not “recover by itself” and is effectively criterion C. Estimate the common-mode dV/dt on the cable, then check CMTI (6N137-class ≈ 10 kV/µs min is modest) and layout capacitance across the barrier. Fixes: an input RC filter and debouncing matched to the signal bandwidth, a coupler with ≥ 25–50 kV/µs CMTI, and a tighter input loop. Retest with the counter monitored.

Additional Resources

Test methods

IEC 60270 (partial-discharge measurement) • IEC 61000-4-2 / -4-4 / -4-5 / -4-6 / -4-3 (immunity test methods) • IEC 61000-6-1 / -6-2 (generic immunity) • JEDEC JESD51 series (thermal measurement).

Where test levels come from

End-product standards: IEC 62368-1 (electric strength test), IEC 61010-1, IEC 60601-1 (dielectric strength, leakage currents), IEC 61800-5-1. Component: UL 1577, IEC 60747-5-5 (see Module 16).

Vendor material

Your coupler vendor’s CMTI test-circuit description, isolation certificate and reliability report; the Hi-Pot tester manufacturer’s application guide for AC vs DC testing.