Lesson 3/1718%
MODULE 03

Optocoupler Construction

How optocouplers are physically built: die technologies for emitter and detector, co-planar vs stacked die arrangements, isolation barrier materials and their partial-discharge behavior, package families from 4-pin DIP to wide-body SO16, and a walk through the manufacturing and test flow.

Learning Objectives

After completing this module, you will be able to:

Describe LED and detector die technologies and their trade-offs
Compare co-planar, stacked, and reflective coupling constructions
Evaluate isolation barrier materials (polyimide, silicone, epoxy)
Select package types for creepage, clearance, and assembly requirements
Outline the manufacturing and production-test sequence
Where this fits. Module 1 treated the optocoupler as a black box — LED in, light across a barrier, detector out. This module opens the box. You will see why the physical construction decides CTR, speed, isolation rating, common-mode immunity and package size, so that when Module 4 (Working Principle) derives the device physics and Module 6 (Parameters) quantifies the datasheet, every number has a physical cause you can picture. Board-level spacing is covered in Module 11 (PCB Design Guidelines).
All illustrations and animations on this page are schematic teaching drawings, not to scale. Numerical values are representative of common parts; always confirm against the current datasheet of the exact part number you buy.

Strip away the plastic and every optocoupler contains the same five functional elements: an emitter die (an infrared LED), a detector die (a silicon photo-sensitive device), two electrically separate lead frames that carry them, an optical path that lets light travel from one die to the other, and an insulation system that prevents anything but light from making the trip. The package around them provides mechanical protection, blocks ambient light, and sets the external creepage and clearance distances.

Cross-section of a face-to-face optocoupler: an infrared LED die on the input lead frame at the bottom, a phototransistor die on the output lead frame at the top, an insulating film between them, all inside an inner clear mould and an outer opaque mould
Figure 1. Cross-section through the optical path of a face-to-face (stacked) phototransistor optocoupler. The two lead frames never touch; the only thing that crosses from left to right is infrared light. The distance straight through the solid insulation between the two sides is the DTI.
Input pins
→
Input lead frame
→
LED die
→
Photons through the barrier
→
Detector die
→
Output lead frame
→
Output pins

The barrier is a system, not a single layer

It is tempting to point at the thin film between the dies and call it “the isolation barrier”. In reality a certification body evaluates the whole insulation system: the film (if any), the clear silicone or epoxy that fills the optical path, the interfaces where those materials meet, the outer moulding compound, and the external surfaces between the pins. A perfect film is worthless if moisture can wick along a poorly bonded interface from one lead frame to the other. That is why component standards such as IEC 60747-5-5 test the finished part (hi-pot, partial discharge, insulation resistance) rather than the raw materials.

Interactive: Exploded View of the Package

Drag the slider (or press Play) to pull the package apart layer by layer. Click or tap any layer to read what it does and what can go wrong with it.

Exploded view of an optocoupler package showing six layers
Select a layer

Click any layer of the exploded package. The information panel explains its material, its job, and its typical failure modes.

Design trap — “it’s isolated, it has an optocoupler”. The optocoupler only guarantees isolation inside its own body. The moment you route a trace, place a via or a Y-capacitor, or mount a heatsink across the gap between its input and output pins, the part’s internal construction is irrelevant: your board now sets the barrier.

The emitter is almost always an infrared LED made from a III–V compound semiconductor. When forward current flows, electrons and holes recombine at the junction and give up their energy as photons. The photon energy, and therefore the wavelength, is set by the energy gap the carriers fall across:

λ = h·c / E  ⇒  λ[nm] ≈ 1240 / E[eV]
  • λ — emission wavelength (nm)
  • h — Planck’s constant, c — speed of light
  • E — photon energy (eV), close to the band-gap energy Eg of the emitting layer

Pure GaAs has Eg ≈ 1.42 eV at room temperature, so band-to-band emission is near 1240 / 1.42 ≈ 870 nm. The two LED families you will meet in optocoupler datasheets both descend from GaAs:

Property GaAs:Si (silicon-doped GaAs) GaAlAs / AlGaAs (heterostructure)
Peak wavelength ≈ 940 nm (Si dopant creates lower-energy states) ≈ 850–880 nm (set by aluminium fraction)
Forward voltage VF ≈ 1.2 V typ, 1.4 V max at 10–20 mA ≈ 1.4–1.6 V typ, up to ≈ 1.8 V max
Optical efficiency Good Higher — carriers confined in a thin active layer
Speed Slow (long carrier lifetime): suits µs-class parts Fast: used where the detector is fast too
Typical use General-purpose phototransistor parts (PC817, 4N35) High-speed logic, gate-driver and linear parts (e.g. HCNR201, IL300)

Representative values. The datasheet’s description line (“GaAs infrared LED”, “AlGaAs LED”) and its VF table tell you which technology a specific part uses.

Left: layer stack of a GaAlAs double-heterostructure LED with p-GaAlAs window, thin active layer, n-GaAlAs cladding and GaAs substrate. Right: silicon NPN phototransistor with a large p-base, small n+ emitter and n-type collector, with the base-collector depletion region highlighted
Figure 2. Inside the two dies. Left: a double-heterostructure LED confines electrons and holes in a thin active layer so that they recombine radiatively. Light leaves through the top and the sides of the die. Right: the phototransistor’s large base area is the light-collecting junction; its gain is what lets CTR exceed 100 %.

Why infrared and not visible light?

Silicon detectors respond best in the near-infrared, peaking at roughly 800–950 nm. GaAs-family LEDs are efficient emitters in exactly that band. Visible LEDs would work, but they would couple less of their power into a silicon detector and are less efficient emitters. The infrared choice also means the outer mould can be opaque black epoxy that blocks ambient visible light.

Graph of relative intensity versus wavelength from 600 to 1150 nm showing the silicon detector response peaking near 900 nm, a GaAlAs LED peak near 870 nm and a GaAs:Si LED peak near 940 nm, both inside the silicon response
Figure 3. Both LED families sit inside the silicon response curve. The overlap between the emitter spectrum and the detector response is one of the factors that multiply together to give CTR (the others are covered in Module 4).

Forward voltage and temperature

The LED’s VF falls by roughly 1.5–2 mV/°C. For a resistor-driven LED this raises IF slightly when hot. That is harmless, but it matters when you calculate worst-case IF from a minimum supply with maximum VF at cold.

Worked example — LED drive for a PC817 from 5 V
Target IF = 10 mA. Datasheet: VF = 1.2 V typ, 1.4 V max (at IF = 20 mA).
  1. Size the resistor for the minimum current case (max VF, min supply 4.75 V): R = (4.75 − 1.4) / 10 mA = 335 Ω → choose 330 Ω.
  2. Check the maximum current case (VF ≈ 1.0 V hot, 5.25 V supply): IF = (5.25 − 1.0) / 330 ≈ 12.9 mA. Well below the 50 mA absolute maximum.
  3. LED dissipation ≈ 12.9 mA × 1.2 V ≈ 15 mW, versus a typical 70 mW input power rating.

Interactive: Emitter–Detector Spectral Match

Move the LED’s peak wavelength and spectral width and watch how much of its output falls where silicon is sensitive. The result is the detector-weighted fraction of emitted power (a simplified model of the spectral part of coupling efficiency).

Photon energy at peak–
Detector-weighted fraction–
Relative to best-case LED–
–

The emitter side of the optocoupler family is fairly uniform. The detector side is where the families diverge. Every detector starts with a silicon p–n junction that turns absorbed photons into a photocurrent IPH. What differs is what the die does with that tiny current (typically micro-amps): amplify it with a transistor, square it up with logic, stack it into a voltage that drives MOSFET gates, or use it to fire a thyristor.

Detector die What is on the die Gain / sensitivity Speed class Examples
Phototransistor NPN with a large light-sensitive base–collector junction. Base is bonded out on 6-pin parts. CTR ≈ 20–600 % tr, tf ≈ 2–20 µs (load dependent) PC817, 4N35, TLP785
Photodarlington Phototransistor driving a second transistor on the same die CTR ≥ 500 % (often > 1000 %) Tens to hundreds of µs 4N32, H11B1
Photodiode + transistor Separate photodiode feeding the base of an output transistor. This removes the Miller-multiplied CCB from the light-sensing node. CTR ≈ 7–50 % ≈ 1 Mbit/s 6N135, 6N136
Photodiode + logic IC Photodiode, trans-impedance amplifier, comparator and logic output, often under a transparent Faraday shield Specified as an LED threshold current (a few mA) 10–50 Mbit/s class 6N137, HCPL-2630, TLP2361
Photovoltaic array + MOSFETs A series stack of tiny photovoltaic cells charges the gates of a pair of output MOSFETs (solid-state relay) Specified as LED turn-on current ≈ 0.1–few ms switching AQY210, TLP222
Photo-TRIAC Light-activated bidirectional thyristor, with optional zero-crossing inhibit circuit LED trigger current IFT (5–15 mA) Mains-cycle switching MOC3021, MOC3041, MOC3063
Gate-driver IC Photodiode, amplifier and a push-pull output stage rated for amps of peak gate current. Newer parts add UVLO, DESAT and Miller clamp. LED threshold current (a few mA) Sub-µs propagation delay HCPL-3120, TLP250, ACPL-332J

Speed and gain columns are order-of-magnitude guides. Module 5 (Types) walks through each family with its own characteristic curves.

Why a phototransistor is slow: Miller capacitance

A phototransistor needs a large base–collector junction to catch light. A large junction means a large capacitance CCB. The collector swings by volts while the photocurrent charging that capacitance is only micro-amps, and the transistor’s gain multiplies the effective capacitance (the Miller effect). This construction choice is the root of the microsecond switching times. Splitting the die into a photodiode plus a separate transistor (6N135/6N136) keeps the light-sensing node at an almost constant voltage, and gains roughly an order of magnitude in speed at the cost of CTR.

Pro tip — the base pin. On 6-pin phototransistor parts (4N35 and similar) the base is bonded out. A resistor RBE from base to emitter (typically 100 kΩ–1 MΩ) removes stored charge faster and shunts dark and displacement current, which speeds turn-off and improves noise immunity. The cost is some lost CTR. Left unconnected, the base pin is a high-impedance node that picks up noise. 4-pin parts such as PC817 do not bring the base out at all.

Dark current: the detector’s leakage

With the LED off, a phototransistor still conducts a small collector–emitter leakage current ICEO (“dark current”). It is typically nanoamps at 25 °C (datasheet maxima of tens of nA are common), but like all silicon junction leakage it rises roughly exponentially with temperature (a common rule of thumb is a doubling every ≈ 10 °C). With a high-value pull-up resistor at 100 °C+, dark current can erode your logic-high margin. Check the ICEO vs TA curve.

Worked example — is dark current a problem?
A 4N35-class output pulls up to 5 V through RL = 100 kΩ. Assume ICEO = 50 nA at 25 °C and a doubling every 10 °C.
  1. At 85 °C: 50 nA × 26 = 3.2 µA.
  2. Voltage drop in RL = 3.2 µA × 100 kΩ = 0.32 V → output high ≈ 4.68 V. Still a valid logic high.
  3. At 105 °C: 12.8 µA → 1.28 V drop → ≈ 3.7 V. Now marginal for 5 V CMOS (VIH = 3.5 V). Use RL ≤ 10 kΩ or the real curve from the datasheet.

Given two dies on two separate lead frames, the manufacturer has to decide how to point one at the other. Three arrangements dominate. Each is a different trade-off between how much light arrives (which sets CTR), how far apart the two conductors are (which sets isolation), and how much they “see” each other electrically (which sets input–output capacitance and common-mode immunity).

Three panels. A: co-planar construction with LED and detector side by side under a reflective dome, light reaching the detector by reflection. B: face-to-face construction with the detector directly above the LED and an insulating film between. C: face-to-face with only clear silicone in the gap, and a void marked as a partial discharge risk
Figure 4. The three common coupling constructions. Co-planar parts use a long internal path and rely on reflection. Stacked parts face the dies directly across a film or silicone layer.
Construction How light gets across Strengths Weaknesses
Co-planar / reflective dome Dies side by side on one plane; a clear dome with a white reflective outer surface bounces light onto the detector Long internal isolation path, low CIO, very high isolation ratings possible Lower coupling efficiency, so lower CTR or more IF needed for the same output
Face-to-face with insulating film Dies stacked facing each other; a transparent polyimide film between Highest coupling efficiency. The film is a pre-qualified, uniform barrier with a defined DTI. Larger overlapping area, so higher CIO. The film–silicone interfaces must be void-free.
Face-to-face, silicone gap Dies stacked facing each other; the gap is filled with clear silicone High efficiency, simple, low cost Isolation depends on gap control and void-free filling. Voids cause partial discharge (Section 5).
Animation: photons stream from an LED in two constructions. In the face-to-face construction many photons reach the detector directly above. In the co-planar construction photons must reflect off the dome and fewer land on the detector
Animation 1. Same LED, same detector, different geometry. The live counters show what fraction of the emitted photons land on the detector in each construction. This is a simplified 2-D ray model: absolute numbers are illustrative, but the ranking is real.

The hidden capacitor: CIO and common-mode transients

Two lead frames and two dies separated by an insulator form a small capacitor, the input–output capacitance CIO. It is typically well under a picofarad to about 1 pF, which sounds harmless until the voltage between the two grounds moves quickly. Every volt per second of common-mode slew pushes a displacement current through the barrier:

iCM = CIO × dVCM/dt
  • iCM — displacement current injected across the barrier (A)
  • CIO — input-to-output capacitance (F)
  • dVCM/dt — slew rate of the voltage between the input and output grounds (V/s)
Worked example — 1 pF meets a fast switching node
CIO = 1 pF, and the output side sits on a half-bridge switch node slewing 10 kV/µs (1010 V/s).
  1. iCM = 1 × 10−12 F × 1010 V/s = 10 mA.
  2. A phototransistor’s photocurrent is only micro-amps (e.g. IC = 2 mA at hFE ≈ 400 gives IPH ≈ 5 µA). Even a small fraction of 10 mA landing on the base node is a false “light” signal thousands of times larger than the real one.
  3. This is why high-CMTI parts use constructions that minimise and steer this current: a transparent conductive Faraday shield over the detector, tied to output ground, plus low-impedance photodiode front ends.

Calculator: Barrier Displacement Current

Worst-case assumption: the whole CIO current reaches the sensitive detector node (a shielded part diverts most of it).

Displacement current iCM–
Ratio iCM / IPH–
Charge per edge Q = CIO·ΔV–
Edge duration ΔV / (dV/dt)–
–

Design trap — “it passed hi-pot, so it will survive the inverter”. Hi-pot tests the barrier’s strength at 50/60 Hz. Common-mode immunity is about its capacitance at kV/µs. A part can hold off 5 kVrms and still glitch on every edge of a SiC half-bridge. CMTI is a separate datasheet line; see Module 6.

Four materials do most of the insulating inside an optocoupler. They must be transparent to near-infrared (where they sit in the optical path), bond reliably to each other and to metal, survive solder reflow, and hold off kilovolts for decades without eroding.

Material Role Dielectric strength (representative) Strengths Watch-outs
Polyimide film Thin transparent sheet between facing dies ≈ 150–300 kV/mm (thin-film test values) Very high strength, uniform thickness, stable to > 300 °C, pre-tested before assembly Adhesion at film edges; moisture absorption; slight IR loss
Clear silicone Optical gel or elastomer filling the light path ≈ 15–25 kV/mm Excellent IR transparency, stays compliant over temperature (low stress on wire bonds) Voids and bubbles during dispensing; weaker bond to epoxy
Clear epoxy Inner transparent mould (light pipe) in double-mould parts ≈ 15–30 kV/mm Rigid, precise geometry, good light guide Higher stress on dies; yellowing and cracking at high temperature
Opaque mould compound Outer body; defines external surfaces ≈ 15–30 kV/mm Blocks ambient light; mechanical strength; low moisture uptake Its CTI sets the material group used for external creepage
For comparison: air Clearance between pins ≈ 3 kV/mm (mm-scale gaps, sea level) Self-healing after a flashover Falls with altitude; needs large distances

Dielectric strength depends strongly on thickness, test method, temperature and humidity. Use these values only to build intuition; the component’s certified ratings (VIORM, VIOTM, VISO) are what you design to.

Breakdown strength is not the design limit — partial discharge is

If polyimide holds hundreds of kV/mm, why is a part with a 0.4 mm DTI only rated for ≈ 900 Vpeak continuous working voltage? Because insulation rarely fails by clean instantaneous breakdown in service. It fails by partial discharge (PD) and slow erosion. Any gas-filled void, crack or delaminated interface inside the solid sees a higher field than the surrounding material. For a thin disc-shaped void across the field, it is roughly εr times higher (εr ≈ 3–4 for epoxy or polyimide). And gas breaks down far more easily than solid. Each AC half-cycle above the PD inception voltage produces tiny discharges that carbonise and erode the void walls. Over months or years this grows “electrical trees” that eventually bridge the barrier.

Animation: two insulation samples between electrodes under a rising AC voltage. The void-free sample shows no discharge; the sample with a gas void flashes each half-cycle once the voltage exceeds the partial discharge inception level, with pulses marked on a waveform trace
Animation 2. Same material, same thickness. As the AC test voltage ramps up, the sample with a microscopic gas void starts discharging every half-cycle once the inception level is crossed. The void-free sample stays quiet. This is exactly what the production PD test of IEC 60747-5-5 screens for (Section 9).
Worked example — field across a 0.4 mm barrier
A reinforced part has DTI = 0.4 mm, VIORM = 890 Vpeak and VIOTM = 6000 Vpeak (representative values for a wide-body optocoupler).
  1. Continuous working stress: E = 890 V / 0.4 mm ≈ 2.2 kV/mm, about 1 % of polyimide’s short-term strength.
  2. Transient over-voltage: E = 6000 V / 0.4 mm = 15 kV/mm. This is still below bulk breakdown, but only for the specified short duration.
  3. The large apparent margin is deliberate. It keeps any residual void below PD inception over 20+ years, at temperature and humidity. That margin is what VIORM certifies.

Calculator: Electric Field Across the Barrier

Compare the average field in the insulation with the material’s representative short-term strength. Remember: the certified working voltage, not this ratio, is your design limit.

Average field E = V / d–
Utilisation of short-term strength–
Field inside a thin void (≈ εr·E)–
–

Pro tip — ask how the barrier is qualified. For a reinforced application, ask the vendor (or read the certificate) for: DTI, the insulation material, whether 100 % production PD testing is performed (IEC 60747-5-5 method b), and the partial-discharge limit (typically < 5 pC). A UL 1577 withstand rating alone does not tell you any of this.

Safety standards describe an isolation barrier with three independent distances. The package construction fixes all three for the component. Your PCB layout can only make the external ones worse, never better.

Side view of an SMD optocoupler on a PCB showing clearance as the straight air path between input and output leads, creepage as the path along package and board surfaces between pads, and DTI as the internal distance through solid insulation between the two lead frames
Figure 5. Clearance (through air), creepage (along surfaces) and DTI (through solid insulation) are three different distances, protecting against three different failure mechanisms.
Clearance — protects against flashover

Shortest distance through air between conductors on the two sides. Sized for the peak transient (impulse) voltage from the overvoltage category, corrected for altitude above 2000 m.

Creepage — protects against tracking

Shortest distance along insulating surfaces. Sized for the rms working voltage, pollution degree and the material group (CTI) of the surface. Contamination plus moisture slowly forms carbon tracks.

DTI — protects against solid breakdown

Shortest distance through solid insulation inside the package. Many end-product standards require ≥ 0.4 mm for supplementary or reinforced solid insulation. Thin-sheet film constructions may instead qualify by layer-count and type testing.

Material group: why the mould compound’s CTI matters

Required creepage depends on how easily the insulating surface tracks, measured as the Comparative Tracking Index (IEC 60112) and grouped as follows:

Material group CTI range Typical where you meet it
ICTI ≥ 600Special high-CTI mould compounds and laminates
II400 ≤ CTI < 600Better mould compounds; high-CTI FR-4 grades
IIIa175 ≤ CTI < 400Many optocoupler bodies; standard FR-4
IIIb100 ≤ CTI < 175Lowest-grade materials

The optocoupler datasheet states its body’s CTI or material group in the “insulation characteristics” table. Use the lower of the package and PCB groups for a creepage path that runs across both surfaces.

Worked example — does the package spacing meet a 230 V reinforced requirement?
Product: 230 VAC mains, working voltage 250 Vrms, overvoltage category II, pollution degree 2, material group IIIa, reinforced insulation needed. Values from the IEC 60664-1 tables (confirm against the edition and end-product standard you certify to):
  1. Creepage, basic, 250 V, PD2, group III → 2.5 mm. Reinforced = 2 × basic = 5.0 mm.
  2. Rated impulse for OVC II at 230 V = 2.5 kV → basic clearance 1.5 mm. Reinforced uses the next impulse step (4 kV) → 3.0 mm.
  3. Standard 7.62 mm DIP (≈ 7 mm external): passes with margin. SOP-4 (≈ 5 mm): meets it exactly, with no margin for board-level losses. Narrow SO-8 (≈ 4 mm): fails.
  4. Same product in an industrial cabinet (pollution degree 3): basic creepage becomes 4.0 mm, reinforced 8.0 mm. Only the wide-lead DIP, stretched SO or wide-body SO-16 packages now qualify.
Design trap — internal vs external. Internal distances (along the die-to-film interface, through the film) are covered by the component’s certification, provided you use it within its ratings. External creepage and clearance must still be checked against your end-product standard, pollution degree and altitude. Medical equipment (IEC 60601-1, 2 × MOPP) typically needs 8 mm at 250 V, which rules out most standard packages. See Module 16.

The same die pair is often sold in several packages. The package decides the external creepage and clearance, the maximum certifiable working voltage, the assembly process, and the board area. Figure 6 lines up the common families at the same scale.

Seven optocoupler packages drawn to the same scale in top view on a 1 mm grid: 4-pin DIP, 6-pin DIP, 6-pin DIP with 400-mil wide leads, SOP-4, narrow SO-8, stretched SO-6/SO-8, and wide-body SO-16, each annotated with lead span and representative creepage
Figure 6. Package families to scale. What increases creepage is the lead span across the body, not the pin count. “Stretched” SO packages keep a small footprint along the rows while pushing the two rows apart to reach ≥ 8 mm.
Package Mount Creepage / clearance (typ.) Typical DTI Typical VIORM range Board area (approx.) Notes

Representative values across several vendors. The same package outline can be certified to different values by different manufacturers. Always copy the certified figures from the exact part’s datasheet into your safety file.

Interactive: Package Comparator

Enter your spacing and assembly requirements. The table above highlights packages that pass (green edge) and dims those that fail, and the summary recommends the smallest passing package.

Packages passing–
Smallest passing package–
Its creepage margin–
–

Beyond spacing: the other package decisions

DIP vs SMD versions of the same part

Many DIP parts come with gull-wing leads for reflow (often an “S” or “SMD” ordering option) and a 400-mil wide-lead option (“W”, “T”, option 6 — vendor specific). Isolation ratings can differ between options.

Channels per package

Dual and quad packages save area. However, adjacent channels inside one body are not isolated from each other to the same level (or at all) unless the datasheet states it.

Thermal and power

Smaller packages have higher RθJA and lower total power ratings. Gate-driver parts pushing amps of peak current need the wider bodies partly for heat, not only for spacing.

Pin-compatible is not certificate-compatible

A second-source part in the same outline may have a different CTI, DTI or VIORM. Re-check the insulation table before approving an alternate.

The lead frame is the stamped or etched metal skeleton that carries the dies and becomes the pins. Its material and finish matter to you because they set solderability, whisker risk and how the package survives your reflow profile.

Aspect Common choices Why it matters to the board designer
Lead-frame alloy Copper alloys; iron–nickel (Alloy 42) in some packages Copper conducts heat better; Fe–Ni matches silicon expansion but is less solderable and magnetic
Lead finish Matte tin; NiPdAu pre-plated frames Solderability and shelf life; tin whisker mitigation in long-life products
Die attach Conductive (silver-filled) epoxy Thermal path from the dies to the pins
Wire bond Gold (or copper) wire, ≈ 25–30 µm Wires sit in the compliant silicone; harsh thermal cycling can fatigue them
Moisture sensitivity MSL rating per J-STD-020 (SMD parts) Absorbed moisture flashes to steam in reflow and can delaminate internal interfaces. Delamination can open an internal creepage path.
Design trap — reflow and the barrier. Popcorning or micro-delamination after an out-of-spec reflow, or reflowing a DIP part that is rated for wave or hand soldering only, may not show up as an electrical failure on the line. It can silently reduce the barrier’s PD performance. Respect the datasheet’s soldering conditions and MSL floor life, and bake per J-STD-033 when it is exceeded.
Pro tip. Through-hole DIP datasheets usually give a lead soldering limit such as 260 °C for 10 s at a stated distance from the body. That is a wave or hand-soldering rating, not permission to run the DIP through a full convection reflow profile. Use the SMD (gull-wing) ordering option for reflow lines.

LED and detector wafers are fabricated separately. Often they come from different fabs and different materials systems. They meet for the first time in back-end assembly. Watch the sequence below, then read how each step shows up in the datasheet.

Animation of eight assembly steps: lead frames, die attach, wire bond, insulating film, inner clear mould, outer mould, trim and form, and 100 percent test with a pass result and CTR rank B
Animation 3. Assembly of a face-to-face, double-mould optocoupler in eight steps. A progress strip at the top shows the current step.
Step What happens What it controls
1. Wafer fab & dicingLED (III–V) and detector (Si) wafers probed, sawn into diesEmitter efficiency, detector gain → CTR spread
2. Die attachDies bonded to their lead-frame padsThermal path, die position (optical alignment)
3. Wire bondDie pads connected to lead fingersReliability under thermal cycling
4. Barrier / optical pathFilm placed or silicone dispensed; frames brought into positionDTI, voids, coupling efficiency
5. MouldingInner clear and outer opaque transfer mouldingLight pipe, ambient-light rejection, external creepage
6. Trim, form, plateTie bars removed, leads formed (DIP or gull-wing)Lead span, which sets external creepage and clearance
7. Isolation test100 % hi-pot and (for VDE/IEC-certified parts) PD testScreens barrier defects
8. Electrical test & rankVF, leakage, VCE(sat), CTR measured; parts sortedCTR rank bins, datasheet limits

Two different production isolation tests

UL 1577 withstand (hi-pot)

The rating VISO (e.g. 5000 Vrms) is a 1-minute type-test value. In production each part is typically stressed at ≈ 1.2 × VISO for 1 s. Passing proves the barrier withstands a short over-voltage today. It says nothing about decades at the working voltage.

IEC 60747-5-5 partial discharge

For parts certified with a working voltage VIORM, every unit is tested at VPR = 1.875 × VIORM for 1 s (method b) with a PD limit of < 5 pC. Sample and type tests use a longer duration at a lower factor (method a, 1.6 × VIORM). This is the test that screens the voids from Section 5.

Factors as commonly printed in optocoupler datasheets’ insulation tables. The governing values are in the standard edition cited on the part’s certificate.

Animation of parts moving along a production line through nine stations; a few parts are rejected at hi-pot and the rest are sorted into CTR rank bins A, B, C and D with running counters
Animation 4. Every part is isolation-tested; a small fraction is scrapped. Survivors are measured and dropped into CTR rank bins, which is why one part number can ship with very different CTR.

CTR binning: what the rank letter buys you

Coupling efficiency, LED efficiency and detector gain all vary from lot to lot, so raw CTR spreads over nearly an order of magnitude. Rather than scrap that spread, manufacturers measure every part and sell it in guaranteed rank windows.

Histogram of CTR values in a production lot from about 50 to 700 percent, with overlapping rank windows A 80 to 160 percent, B 130 to 260, C 200 to 400 and D 300 to 600, and the unranked specification 50 to 600 percent
Figure 7. One process, many ranks. The rank windows overlap, so a part testing at 250 % could legally ship as rank B or rank C. Unranked parts are only guaranteed the full 50–600 % span.
Worked example — what does ordering a rank save?
Requirement: guarantee IC ≥ 1 mA at end of life. Budget ×0.5 for LED ageing and ×0.8 for temperature (Module 9 refines these).
  1. Unranked PC817 (CTRmin = 50 %): IF = 1 mA / (0.5 × 0.5 × 0.8) = 5.0 mA.
  2. Rank B (CTRmin = 130 %): IF = 1 mA / (1.3 × 0.5 × 0.8) ≈ 1.9 mA, a 62 % cut in LED current. Lower IF also slows LED ageing.
  3. The saving is only real if the ordering code in your BOM locks the rank. A generic “PC817” line lets purchasing buy any rank.

Manufacturers rarely publish cross-sections, but the construction leaves fingerprints all over the datasheet. You can infer most of this module’s content from five places:

Datasheet location What it reveals about construction
Description line / block diagram LED material (GaAs, AlGaAs), detector type, Faraday shield (“internal shield”)
Insulation characteristics table External creepage and clearance, DTI, CTI and material group, VIORM, VIOTM, VPR test factors
Electrical table: CIO, RIO Face-to-face vs co-planar (CIO), barrier quality (RIO ≈ 1011 Ω or more)
CMTI / CMR specification Shielding and detector front-end design
Ordering information & package drawing CTR ranks, lead-form options, wide-lead variants, MSL and soldering limits

Questions to ask a vendor for a safety-critical barrier

1. Construction

Co-planar or face-to-face? Film, silicone, or both?

2. DTI and material

Minimum DTI and the insulation material specification.

3. PD testing

Is 100 % production PD testing done (method b)? Limit in pC?

4. Certificates

UL 1577 file number and VDE/IEC 60747-5-5 certificate, with the ordering options they cover.

5. Ageing data

CTR-degradation curves vs IF and temperature (needed in Module 9).

6. Change control

Will you be notified (PCN) of assembly-site, material or construction changes?

Common construction-related field failures

Gradual CTR loss

LED light-output degradation, accelerated by high IF and temperature. Module 12.

Barrier breakdown after years

PD erosion from voids or delamination, often after reflow damage or repeated hi-pot testing.

Intermittent output glitches

Common-mode displacement current through CIO in unshielded parts near fast switch nodes.

Surface tracking between pins

External creepage too small for the real pollution degree; contamination and condensation.

Five elements

Emitter die, detector die, two separate lead frames, an optical path, and an insulation system.

Infrared by design

GaAs (≈ 940 nm) and GaAlAs (≈ 850–880 nm) LEDs match silicon’s peak response.

Detector sets the family

Phototransistor, Darlington, photodiode + logic, PV array, photo-TRIAC, gate driver: same LED, different die.

Construction is a trade-off

Face-to-face gives high CTR; co-planar gives a long internal path and low CIO.

CIO × dV/dt

1 pF at 10 kV/µs is 10 mA of displacement current. Shielding, not isolation voltage, fixes CMTI.

PD, not breakdown

Working-voltage ratings exist to keep voids below partial-discharge inception for decades.

Three distances

Clearance (air), creepage (surface) and DTI (solid) protect against different failures.

Package sets external spacing

Lead span, not pin count, determines creepage; ≥ 8 mm needs wide-lead or stretched packages.

Lock the rank

CTR ranks are measured after assembly; your BOM must name the rank to get its guarantee.

Construction & package design checklist

Tick items as you review a design. Your ticks are saved in this browser only. Use your browser’s print function for a sign-off copy.

Four parts: multiple choice, true/false, a matching exercise and three engineering scenarios. Score 80 % on the multiple choice to pass the module.

Part A — Multiple Choice

Question 1 of 12  •  Score: 0/12

Part B — True or False

Score: 0/8

Part C — Match the Term to Its Meaning

Drag each term onto its definition, or click a term and then click a definition. Wrong drops bounce back with a hint.

Placed: 0/6

Part D — Engineering Scenarios

Scenario 1 — The SOP-4 that moved into a factory
A 230 VAC product (working voltage 250 Vrms, OVC II) uses an SOP-4 optocoupler with 5.0 mm external creepage as its reinforced barrier. It passed certification for office use (pollution degree 2, material group IIIa). Marketing now wants to sell it for installation in industrial control cabinets (pollution degree 3). Is the part still acceptable, and if not, what do you change?
Analysis. At pollution degree 3, group III material and 250 V, IEC 60664-1 basic creepage is 4.0 mm, so reinforced = 8.0 mm. The SOP-4’s 5.0 mm fails by 3 mm. Clearance (3.0 mm for 4 kV impulse) is still satisfied. Fix: move to a package with ≥ 8 mm creepage (stretched SO-6/SO-8, 400-mil wide-lead DIP, or wide-body SO-16). Re-route the PCB so board creepage also reaches 8 mm, which may need a slot (Module 11). Alternatively, raise the material group: a group I body and board would shorten the requirement, but that is rarely practical for both surfaces.
Scenario 2 — Glitches on a SiC half-bridge
A prototype uses a PC817 (CIO ≈ 0.6 pF typ, no shield) to send a fault signal from the high-side gate-drive domain of an 800 V SiC half-bridge. The switch node slews at 50 kV/µs, and the fault line toggles falsely on many edges. Hi-pot at 5 kVrms passes. Explain the failure using construction concepts and propose a fix.
Analysis. iCM = 0.6 pF × 50 kV/µs = 30 mA for the ≈ 16 ns of each 800 V edge (800 V / 50 V/ns). That is three to four orders of magnitude above the phototransistor’s micro-amp photocurrent. With no Faraday shield, part of it reaches the base node and is amplified by hFE into a false output pulse. Hi-pot passing is irrelevant: it tests strength, not capacitance. Fix: use a shielded high-CMTI part (a gate-driver or logic optocoupler with CMTI comfortably above 50 kV/µs, or a digital isolator, see Module 15). Add output filtering or debounce sized to the edge duration. Keep the output-side reference tied tightly to the local domain ground.
Scenario 3 — The rank that purchasing changed
A design drives a PC817 at IF = 2 mA and needs IC ≥ 1 mA at end of life (ageing ×0.5, temperature ×0.8). The engineer assumed rank C (200–400 %). The BOM line reads only “PC817”, and the production build uses unranked parts. Does it still work?
Analysis. Rank C: 2 mA × 2.0 × 0.5 × 0.8 = 1.6 mA, which passes with 60 % margin. Unranked (50 % min): 2 × 0.5 × 0.5 × 0.8 = 0.4 mA, which fails. Units at the bottom of the spread will not saturate the output at end of life. Fix: put the full ordering code with the rank in the BOM and approved-vendor list, or redesign for the unranked minimum (IF = 1 / (0.5 × 0.5 × 0.8) = 5 mA, accepting faster LED ageing). Ranks are sorted after assembly (Section 9), so the rank really is a different product.

Additional Resources

Datasheets worth reading for construction clues

PC817 (4-pin DIP, CTR ranks) • 4N35 (6-pin DIP, base pin) • 6N135 / 6N136 (split photodiode) • 6N137 (logic output, shield) • TLP2361 (SO6L stretched package) • ACPL-332J (wide SO-16 gate driver) • HCNR201 (AlGaAs LED, dual detector). Read each one’s insulation table.

Standards referenced

IEC 60747-5-5 (optocoupler insulation characteristics and PD test) • UL 1577 (isolation withstand) • IEC 60664-1 (creepage, clearance, pollution degree) • IEC 60112 (CTI) • J-STD-020 / J-STD-033 (MSL, handling and bake).

Application notes

Broadcom “Regulatory Guide to Isolation Circuits” • vendor application notes on optocoupler CMR/CMTI and shielding (Broadcom, Toshiba, Vishay, Renesas) • vendor reliability reports with LED ageing data.

Keep learning

Module 4 turns this construction into physics (CTR, switching). Module 6 quantifies every parameter. Module 11 carries the spacing onto the PCB. Module 16 covers the standards behind the ratings.