Lesson 6/1735%
MODULE 06

Optocoupler Parameters

Every number on the datasheet that matters, treated quantitatively: CTR and its dependencies, the full isolation voltage family, forward-current limits, propagation delay and pulse-width distortion, common-mode transient immunity (CMTI), and thermal behavior.

Learning Objectives

After completing this module, you will be able to:

Define and apply every key optocoupler parameter
Compute worst-case CTR across current, temperature, and life
Interpret CMTI ratings for switching converter environments
Budget power dissipation and junction temperatures
Build a parameter checklist for design reviews
Where this fits. Module 4 explained why CTR, speed and saturation behave as they do; Module 5 introduced the families. This module goes parameter by parameter through the numbers you will find on a datasheet: what each one means, the conditions it is measured under, and how to turn it into a worst-case design value. Module 7 (Reading the Datasheet) then shows where they live on a real sheet, and Module 9 (Derating) extends CTR to end of life.
Illustrations and animations are original teaching drawings, not to scale. Values marked representative are typical of common parts; always confirm against the current datasheet or standard you design to.

Every optocoupler datasheet groups its numbers the same way. Knowing the groups lets you check a design systematically instead of hunting for the one number that seems relevant:

GroupParametersQuestion it answers
TransferCTR, IF threshold (logic parts), CTRsatHow much output do I get per unit of input?
IsolationVISO, VIORM, VIOTM, VIOSM, VPR, RIO, CIOWhat voltage can the barrier stand, for how long?
Input (LED)IF, IFP, VR, VF, PDHow hard may I drive the LED?
OutputVCEO, VECO, IC, PC, ICEO, VCE(sat)What can the output switch and survive?
Timingtr, tf, tPHL, tPLH, PWD, tPSKHow fast, and how accurately in time?
Common-modeCMTI (CMH, CML)Will fast ground shifts corrupt the output?
ThermalPtot, RθJA, TJ, derating curvesWill it overheat at my ambient temperature?
Pro tip — the three columns rule. Absolute maximum ratings are survival limits, never design points. Electrical characteristics give min/typ/max at stated test conditions. Design with the min or max column that hurts you, corrected from the test conditions to yours. Typicals are for understanding, not for guarantees.

CTR = IC/IF × 100 %, measured at stated IF, VCE and TA (typically 5 mA, 5 V, 25 °C). The datasheet minimum applies only at that point. Module 4 showed why CTR moves with current, temperature and VCE; Module 9 adds ageing. Here we put them together into one worst-case number.

CTREOL = CTRmin,bin × kIF × kT × kVCE × kage    ⇒    IF,required = IC,required / CTREOL
  • kIF — from the normalised CTR–IF curve at your IF
  • kT — from the CTR–TA curve at your worst temperature (hot or cold)
  • kVCE — CTR reduction at your VCE (switching designs live near VCE(sat))
  • kage — end-of-life factor from ageing data (0.5 is a common conservative choice)
CTR spec lineTypical test conditionUse it for
CTR (bin min/max)IF = 5 mA, VCE = 5 V, 25 °CLinear/active designs; starting point for all
CTRsat or VCE(sat) at IF/ICe.g. IF = 20 mA, IC = 1 mASwitching designs: guarantees a saturation point
CTR at low IFe.g. IF = 1 mALow-power designs (some parts specify it)
CTR ratio / symmetryAC-input partsEqual pulses from both LEDs
Worked example — worst-case IF for a 1 mA output
PC817 rank B (CTRmin 130 %), operating at IF near 3 mA (kIF 0.9), up to 70 °C (kT 0.8), near saturation (kVCE 0.9), 10-year life (kage 0.5).
  1. CTREOL = 130 % × 0.9 × 0.8 × 0.9 × 0.5 = 42 %, less than a third of the headline figure.
  2. IF,required = 1 mA / 0.42 ≈ 2.4 mA. Choose 3 mA, which also confirms the kIF assumption.
  3. With an unranked part (50 % min) the same chain gives 16 % and needs 6.2 mA. Ordering the rank saves LED current and life.

Calculator: Worst-Case CTR

Multiply the datasheet minimum by each correction factor; the bar chart shows where the CTR goes.

CTREOL (worst case)–
Required IF = IC / CTREOL–
Loss vs datasheet minimum–
–

No single “isolation voltage” exists. A barrier is rated for several stresses of very different duration, and the allowed voltage falls as the duration grows. Mixing up rms and peak, or test and working ratings, is the most common isolation mistake in design reviews.

Horizontal bar chart comparing V_IORM 890 V peak, V_PR 1669 V peak, V_ISO 5000 V rms equal to 7071 V peak, V_IOTM 8000 V peak and V_IOSM 10000 V peak for one representative reinforced optocoupler
Figure 1. One part, five ratings. Only VIORM may be applied continuously. Everything above it is a test or a short event.
SymbolMeaningUnit / durationStandard
VISOWithstand test voltage: no breakdownVrms, 60 s type test (1 s at 1.2× in production)UL 1577
VIORMMaximum repetitive peak working voltageVpeak, continuous for lifeIEC 60747-5-5 / VDE 0884-5
VIOWMWorking voltage expressed as rms (some sheets)Vrms, continuousIEC 60747-5-5
VPRPartial-discharge test voltageVpeak; 1.875×VIORM for 1 s (method b, 100 %); 1.6× (method a, sample)IEC 60747-5-5
VIOTMMaximum transient overvoltageVpeak, secondsIEC 60747-5-5
VIOSMMaximum surge isolation voltageVpeak, 1.2/50 µs impulseIEC 60747-5-5
RIOInsulation resistance input–outputΩ at e.g. 500 V DC (often ≥ 1011–1012 Ω)datasheet
CIOInput–output capacitancepF (≈ 0.5–1 pF typ)datasheet
Vpeak = √2 × Vrms (sinusoidal)    VDC,hi-pot ≈ √2 × VAC,rms
  • A 5000 Vrms VISO therefore stresses the barrier to 7071 Vpeak during the test
  • Compare the peak working voltage (including ripple and switching overshoot) with VIORM
Worked example — a 690 V AC motor drive
Line-to-earth working voltage ≈ 400 Vrms; DC bus up to 1000 V DC during regeneration.
  1. Sinusoidal working peak = 1.414 × 400 = 566 Vpk, but the DC bus reaches 1000 V, so the barrier sees up to 1000 Vpk.
  2. A part with VIORM = 890 Vpk is not sufficient, even though its VISO of 5000 Vrms looks huge.
  3. Choose VIORM ≥ 1140–1230 Vpk (stretched SO, wide SO-16), and confirm VIOTM against the drive standard’s transient requirement.

Calculator: Isolation-Voltage Converter and Check

Converts the headline UL rating into peak and DC terms, and checks your working and transient voltages against VIORM and VIOTM. The certified values and the end-product standard govern; this is a sanity check.

VISO as peak / DC hi-pot equivalent–
UL 1577 production test (1.2 × VISO, 1 s)–
VPR production PD test (1.875 × VIORM)–
Working voltage as peak–
VIORM margin–
VIOTM margin–
–

Design trap — “5 kV isolation, so 1000 V is easy”. VISO is a one-minute withstand test, not a working rating. Continuous operation near the test level erodes the barrier through partial discharge (Module 3). The working rating is VIORM, often 5–8× lower.

The LED is the only part of the optocoupler that wears out, so its ratings deserve respect. Four limits matter:

ParameterTypical value (PC817-class)What happens beyond it
IF (continuous)50 mA abs. max, derated with temperatureAccelerated light-output degradation; junction overheating
IFP / IFM (pulse)Up to ≈ 1 A for µs-scale pulses at low duty (part-dependent)Bond-wire and die damage; only for short pulses at low duty
VR (reverse)5–6 VLED junction breakdown; permanent damage
VF1.2 V typ, 1.4 V max at 20 mA (GaAs)Not a limit, but sets drive-resistor worst case

LED reverse protection

Infrared LEDs break down at only a few volts in reverse. Any input that can see reversed polarity (swapped 24 V field wiring, AC coupling, inductive kick) needs protection. Put a small-signal diode (e.g. 1N4148) in anti-parallel across the LED, or a series diode. The anti-parallel diode clamps reverse voltage to ≈ 0.7 V. The series diode blocks it entirely, at the cost of more headroom.

Worked example — pulsed drive to save power
A sensor interface pulses the LED at 20 mA for 100 µs every 10 ms (duty 1 %).
  1. Average IF = 20 mA × 0.01 = 0.2 mA, so ageing and heating track the average and peak current density, both far below limits.
  2. Check the pulse is within the IFP curve (pulse width vs duty) and that the output (CTR at 20 mA) settles within the 100 µs window: ton of a few µs fits comfortably.

The output transistor has its own voltage, current and power limits, completely independent of the isolation ratings:

ParameterTypical (phototransistor)Design note
VCEO35–80 V depending on vendor/partMust exceed the pull-up supply plus any inductive or line transients
VECO6–7 VReverse voltage on the output: tiny! Protect when the output can be back-driven
IC max50 mAContinuous collector current; also limited by PC
PC (collector power)≈ 150 mW at 25 °CIC × VCE in linear operation adds up quickly
ICEO (dark current)nA at 25 °C, rising steeply hotCheck leakage × pull-up at maximum temperature
VCE(sat)≤ 0.2–0.4 V at stated IF/ICGuaranteed only at its own test condition
Design trap — linear operation heats the output. In an analog or feedback circuit the transistor sits at several volts and a few mA: 5 V × 10 mA = 50 mW, a third of PC before derating. Switching designs dissipate little because VCE(sat) is small.

For phototransistor parts, datasheets give tr/tf/ton/toff at a stated RL (Module 4). For logic and driver parts, four timing numbers describe how faithfully a pulse crosses the barrier:

Timing diagram showing an input LED pulse and two inverted outputs, labelling t_PHL, t_PLH, and the skew between two parts
Figure 2. tPHL and tPLH are measured between 50 % points. Their difference is the pulse-width distortion (PWD); the spread between parts or channels is the skew.
ParameterDefinitionTypical (6N137-class)Limits
tPHL, tPLHInput 50 % to output 50 % (both edges)≈ 20–75 nsLatency; loop delay in control systems
PWD|tPHL − tPLH|≤ ≈ 25–35 nsBit-width accuracy; PWM duty error
tPSK (skew)Spread of delays between parts/channelstens of nsParallel buses (SPI clock vs data), H-bridge dead time
Data rateMaximum signalling rate specified10 MBd (6N137)Usually set by PWD, not by tP
PWD% = PWD / tbit × 100 %    rule of thumb: keep PWD ≤ 10–20 % of a bit (UART sampling tolerance, duty-cycle accuracy)
Animation of a bit stream passing through a coupler with 25 ns of pulse-width distortion at increasing data rates from 0.5 to 20 Mbit/s; at high rates the output bits become noticeably shorter and distorted
Animation 1. The same 25 ns PWD is invisible at 0.5 Mbit/s (1.3 % of a bit) and destructive at 20 Mbit/s (50 %). Data rate is limited by distortion long before delay matters.
Worked example — isolated UART
PWDmax = 35 ns.
  1. At 115.2 kbit/s: tbit = 8.68 µs → 0.4 %: negligible.
  2. At 1 Mbit/s: 1000 ns → 3.5 %: fine.
  3. At 5 Mbit/s: 200 ns → 17.5 %: marginal once the receiver’s own sampling error is added. Choose a lower-PWD part or a digital isolator.

Common-mode transient immunity (CMTI) is the maximum rate of change of voltage between the two grounds that the part tolerates without its output changing state. It is specified separately for output-high (CMH) and output-low (CML), in kV/µs, at a stated common-mode amplitude (e.g. 1000–1500 V).

Diagram of a CMTI test: a common-mode pulse generator connected between input ground and output ground; the LED is held on or off and the output is monitored for glitches
Figure 3. The CMTI test. The LED is held on (CML) or off (CMH) while a fast step is applied between the grounds. Any output excursion past the logic threshold fails the part at that slew rate.
TermMeaning
Static CMTIOutput held in a steady state (high or low) during the transient: the datasheet test
Dynamic CMTITransient occurs while the output is switching (more demanding; specified by some modern parts)
CMH / CMLImmunity with output high / low; the lower one governs
Typical ratingsStandard phototransistor/logic parts: ones to tens of kV/µs; shielded logic and gate-driver grades: 25–50 kV/µs min; newest parts ≥ 100 kV/µs
Animation: a 1000 volt common-mode step with increasing slew rate from 5 to 100 kV per microsecond; below the 25 kV per microsecond rating the output stays low, above it a false high pulse appears
Animation 2. Below its rating the part shrugs off the step. Above it, displacement current through CIO produces a false pulse: a spurious UART bit, a phantom fault, or in a gate driver, shoot-through.

Calculator: CMTI Requirement

dV/dt in kV/µs (= V/ns). The 10–90 % edge covers 80 % of the swing, so the average slope is 0.8·ΔV/tr. Peak slopes can be higher than average: keep margin.

Actual dV/dt = 0.8·ΔV / t10–90–
Required CMTI with safety factor–
Margin (rating / actual)–
–

Design trap — trusting the average slope. SiC and GaN edges are not linear ramps. Peak dV/dt during ringing can be 1.5–2× the 10–90 % average. Measure with a high-bandwidth differential probe before signing off.

Optocouplers dissipate little power, but they sit in hot places (next to power stages, inside sealed enclosures), and their ratings derate with temperature. Two heat sources share one small package: the LED (IF·VF) and the output (IC·VCE).

Ptot = IF·VF + IC·VCE     TJ ≈ TA + Ptot · RθJA
  • RθJA — junction-to-ambient thermal resistance, a few hundred °C/W for small packages
  • Use average power for duty-cycled operation, provided the pulses are short relative to the thermal time constant
Two derating charts versus ambient temperature: allowed LED forward current falling from 50 mA at 25 degrees to zero at 100 degrees, and allowed total, collector and LED power falling similarly
Figure 4. Typical derating: flat to 25 °C, then linear to zero at the maximum rating temperature. At 85 °C only ≈ 20 % of the 25 °C rating remains.
Worked example — hot PLC input
IF = 10 mA (VF 1.2 V), output saturated at 10 mA and 0.3 V, 100 % on, TA = 85 °C, RθJA = 350 °C/W, Ptot 200 mW at 25 °C.
  1. P = 12 mW + 3 mW = 15 mW.
  2. TJ ≈ 85 + 0.015 × 350 ≈ 90 °C.
  3. Allowed at 85 °C: 200 × (100 − 85)/75 = 40 mW. 15 mW is fine, but IF = 10 mA equals the derated 10 mA limit of Figure 4. Reduce IF or pick a part rated to 110 °C.

Calculator: Power Dissipation and Junction Temperature

Currents in mA, voltages in V, RθJA in °C/W. The derating model is linear from 25 °C to zero at 100 °C (representative); substitute your part’s curve.

LED power–
Output power–
Total (average)–
Estimated junction temperature–
Allowed Ptot at TA (derated to 0 at 100 °C)–
–

Min/max, not typ

Design with the limiting column, corrected from the datasheet test conditions to yours.

CTR shrinks

CTREOL = CTRmin × kIF × kT × kVCE × kage, often ≈ 30–40 % of the headline figure.

Peak vs rms

VISO is rms and short-term; VIORM is peak and continuous. Compare peak working voltage with VIORM.

LED is fragile in reverse

VR ≈ 5–6 V: add an anti-parallel diode where polarity can reverse.

Output limits are separate

VCEO, VECO (tiny), IC, PC: check them against the pull-up side, not the barrier.

PWD sets data rate

Keep PWD ≤ 10–20 % of a bit; skew matters for parallel lines.

CMTI is about capacitance

dV/dt = 0.8·ΔV/tr; require 2× margin over the measured slope.

Thermal derating is steep

At 85 °C, many ratings are only ≈ 20 % of their 25 °C values.

Design checklist

Tick items as you review a design. Your ticks are saved in this browser only; use your browser’s print function for a sign-off copy.

Four parts: multiple choice, true/false, a matching exercise and engineering scenarios. Score 80 % on the multiple choice to pass the module.

Part A — Multiple Choice

Question 1 of 10  •  Score: 0/10

Part B — True or False

Score: 0/8

Part C — Match the Term to Its Meaning

Drag each term onto its definition, or click a term and then click a definition.

Placed: 0/6

Part D — Engineering Scenarios

Scenario 1 — The 5 kV part in the 1000 V inverter
A reviewer approves an optocoupler for a 1000 V DC-bus inverter because it is “5 kV rated” (VISO = 5000 Vrms, VIORM = 630 Vpk). Is it acceptable?
Analysis. No. The continuous working stress is up to 1000 Vpk, and VIORM = 630 Vpk is exceeded by 60 %. The 5 kVrms figure is a one-minute withstand test. Running continuously above VIORM invites partial discharge and eventual barrier failure. Fix: choose VIORM ≥ 1140–1230 Vpk with the insulation class the end-product standard demands, and document the working-voltage analysis.
Scenario 2 — Phantom UART bytes near a GaN stage
An isolated UART (6N137-class, CMTI min 10 kV/µs) receives random extra bytes when a nearby GaN half-bridge switches 400 V in 5 ns (10–90 %). Explain and fix.
Analysis. dV/dt = 0.8 × 400 V / 5 ns = 64 V/ns = 64 kV/µs, more than 6× the rating. Each edge injects enough displacement current to toggle the output. Fix: use a part rated ≥ 128 kV/µs (2× margin), e.g. a high-CMTI coupler or a digital isolator (Module 15). Also minimise the capacitance between the switch node and the UART ground, and avoid routing the isolated ground as a large plane under the switch node.
Scenario 3 — The LED that died in the field
A 24 V PLC input with a PC817 works on the bench, but units fail after installation. Returns show open LEDs. Field technicians often swap the input wires during commissioning. What is the likely mechanism?
Analysis. Reversed field wiring puts up to 24 V in reverse across the LED branch. Through the series resistor, the LED sees far more than its VR of 5–6 V, breaks down, and the resulting reverse current and heating destroy it. Fix: add an anti-parallel diode across the LED (clamps reverse voltage to ≈ 0.7 V) or a series blocking diode, and a TVS for surges. Module 10 shows the complete PLC input.

Additional Resources

Standards behind the numbers

UL 1577 (VISO) • IEC 60747-5-5 / VDE 0884-5 (VIORM, VIOTM, VIOSM, VPR) • IEC 60747-17 for digital isolators (Module 16).

Datasheets to study

PC817 (CTR, derating), 6N137 (tP, PWD, CMR), HCPL-3120 / ACPL-332J (CMTI, UVLO, thermal), a reinforced wide-body part’s insulation table.

Application notes

Vendor notes on CMR/CMTI measurement and on designing with propagation delay and PWD (Broadcom, Toshiba, Vishay).