PCB Design Guidelines
Layout is where isolation is won or lost: creepage and clearance by pollution degree and material group, isolation slots and their mechanical trade-offs, ground plane partitioning under the barrier, EMI-aware routing of the isolated interface, thermal and high-speed routing, safety spacing, eight full engineering design examples, and a complete set of interactive calculators and knowledge checks.
A datasheet-perfect optocoupler on a poorly laid-out board is not an isolated circuit — it is a certification failure and a field-return waiting to happen. The schematic decides which component provides isolation; the PCB layout decides whether that isolation actually survives contamination, humidity, altitude, a lightning-induced surge, or four years of vibration. Every isolation-rated number on a datasheet (VIORM, VISO, creepage, clearance, CTI) is a property of the component footprint and the copper around it, not just of the part in the pick-and-place feeder.
⚡ Safety
Creepage, clearance, and slot geometry around the optocoupler are what stand between a user and a mains-referenced primary side. Get the spacing wrong and a certified part becomes an uncertified board.
📡 EMC
Ground plane splits, return-path routing, and loop area around the isolation barrier set radiated and conducted emissions, and the board's immunity to surge and ESD.
🔄 Reliability
Copper-to-copper spacing under contamination and humidity determines whether tracking failure appears in year one or never. Layout is the reliability budget you don't get to revise after tooling.
📄 Product certification
UL/IEC/VDE reviewers measure spacing on the physical board and the Gerber files, not on the schematic. Certification bodies routinely reject boards with a compliant BOM and a non-compliant layout.
∞ Long-term insulation performance
Surface tracking is cumulative and driven by pollution degree, humidity cycling, and voltage stress over the product's lifetime — a layout margin that looks fine on day one can fail after years in the field.
🏭 Manufacturing quality
Minimum slot widths, copper-to-edge spacing, solder mask dams, and panelization tolerances are fabrication realities that must be designed in, not discovered at first-article inspection.
Common failures caused by poor PCB layout
Arc-over across an undersized gap
Copper pours or vias placed closer than the calculated clearance let air ionize under surge or switching transients, punching through the "isolation" instantly and often destructively.
Surface tracking (leakage current growth)
Dust, flux residue, and humidity on the solder mask between primary and secondary pads form a slowly-conducting film. Leakage current rises over months until carbonized tracking bridges the gap permanently.
Noise coupling across the barrier
A ground plane routed under the optocoupler, or a primary/secondary trace run in parallel across the gap, capacitively couples switching noise straight across the barrier the part was there to prevent.
Copper under the barrier
An uninterrupted ground or power pour routed beneath the optocoupler body reduces the effective creepage to whatever thin sliver of solder mask remains — a common first-article safety-review rejection.
Interactive: three ways layout defeats isolation
What is creepage?
Compare that with clearance (Section 3): clearance is the shortest path through air. The two numbers are usually different on the same board — a slot or groove can force the surface path to wind a long way around while the straight-line through-air distance barely changes. Section 1's Electrical Arcing animation shows a clearance (through-air) failure; the Leakage Current animation shows a creepage (surface) failure — the same undersized gap can fail either way depending on what's stressing it.
Why creepage matters
Safety
Creepage is what prevents a slowly-growing carbon track from eventually bridging mains voltage to a user-touchable secondary side.
Long-term reliability
Tracking failure is cumulative and often invisible until it isn't — a board can pass Hi-Pot on day one and fail after 18 months of humidity cycling.
Pollution effects
Real enclosures are never pollution-free: dust ingress, condensation, and outgassing from nearby components all reduce the effective creepage a design "gets for free."
High-voltage systems
Required creepage grows faster than linearly with voltage, which is why 800 V battery-pack designs dedicate visibly more board area to spacing than a 24 V PLC input.
| System | Typical working voltage | Why it matters here |
|---|---|---|
| Single-phase mains (EU/Asia) | 230 VAC | Reinforced insulation to low-voltage secondary is a certification baseline (IEC 62368-1 / IEC 60664-1) |
| Single-phase mains (NA industrial) | 400 VAC (3-phase line-line in many regions) | Higher working voltage pushes creepage requirements into the 5+ mm range for reinforced insulation |
| EV / ESS battery pack | 800 V DC | DC has no zero-crossing to help recovery after a tracking event — standards often demand larger margins than the equivalent AC RMS voltage |
| Medical equipment (patient-connected) | Mains-derived, often 250 V working | IEC 60601-1 adds means-of-patient-protection (MOPP) on top of the base creepage/clearance requirement |
| Industrial control systems | 24–250 V, PD2/PD3 environments | Cabinet dust and moisture push many industrial designs to pollution degree 3 rather than the cleaner PD2 assumed indoors |
Creepage standards
Nearly every product-family standard points back to IEC 60664-1 for the underlying creepage/clearance methodology, then narrows it for the application: IEC 61010 (lab & test equipment), IEC 60601-1 (medical, with added MOPP/MOOP margins), IEC 62368-1 (audio/video/IT, the modern hazard-based standard replacing 60950-1/60065), and UL 840 (the US-harmonized creepage/clearance standard for electrical equipment). Four variables drive every lookup:
| Variable | What it captures |
|---|---|
| Pollution Degree (PD1–PD4) | PD1: sealed/no contamination. PD2: normal indoor (most consumer/office). PD3: conductive pollution possible, condensation likely (industrial cabinets). PD4: continuous conductive pollution (rain, conductive dust). |
| Material Group (I, II, IIIa, IIIb) | Set by the insulating material's CTI. Group I (CTI ≥600) tracks least readily; Group IIIb (CTI 100–175) tracks most readily and needs the most spacing. |
| CTI (Comparative Tracking Index) | Volts at which a standardized test causes tracking failure on the material (IEC 60112). Most FR-4 solder mask/laminate falls in Group IIIa (CTI 175–400) unless specifically rated higher. |
| Altitude correction | Applies to clearance only (thinner air breaks down more easily above 2000 m) — creepage is a surface effect and is not altitude-corrected in IEC 60664-1. |
Interactive creepage lookup & calculator
Creepage improvement techniques (animated cross-sections)
| Creepage | Clearance | |
|---|---|---|
| Path | Along a surface | Straight line through air |
| Degraded by | Contamination, moisture, tracking | Sharp edges (field concentration), altitude, humidity affecting breakdown voltage |
| Improved by | Slots, grooves, staggering, coating | Physical distance, rounding conductor edges, potting |
| Altitude-corrected? | No | Yes, above 2000 m |
Air breakdown
Paschen's Law (conceptual overview): the voltage at which a gas gap breaks down depends on the product of gas pressure and gap distance (p×d), not on distance alone. For a fixed pressure, breakdown voltage first falls as the gap widens from zero (more room for an electron avalanche to develop) before eventually rising again at larger gaps — which is why very small gaps (sub-millimeter, e.g. under thin conformal coating or in micro-connectors) can sometimes break down at surprisingly low voltages. Air ionizes when the local electric field strips electrons from gas molecules faster than they can recombine, creating a conductive channel — an arc.
Altitude
Thinner air above 2000 m has fewer molecules per unit volume, so an electron avalanche needs less voltage to sustain itself — breakdown voltage drops with altitude.
Humidity
Water vapor is more easily ionized in some regimes and also promotes surface conduction, generally lowering the effective withstand margin.
Dust
Conductive or hygroscopic dust bridging a gap effectively shortens it, and can locally concentrate the field at sharp particle edges.
Pressure
Lower pressure (thinner air, whether from altitude or a sealed low-pressure enclosure) lowers breakdown voltage per Paschen's relationship.
Electric field concentration
Clearance calculation
Required clearance is driven by the working voltage the barrier sees continuously, but sized against the impulse (transient overvoltage) withstand the installation can deliver — captured by the overvoltage category (OVC I–IV, how directly the circuit is exposed to the mains transient environment) and derated for pollution degree just like creepage.
An isolation slot is a milled-through cutout in the board between primary and secondary copper. It improves creepage (Section 2) by forcing the surface path down one wall, across the slot floor, and back up the other wall, without requiring extra board area in the direction the slot runs — it barely touches clearance, since the through-air distance across the slot opening changes little. Slots are the standard way to fit reinforced-insulation-grade creepage into a footprint that would otherwise not have room for it.
Slot dimensions
Width is set by the fabricator's minimum routed-slot capability (commonly 0.5–1.0 mm for a standard mill bit); depth equals board thickness (it's a through-cut). Length must clear the full width of the primary/secondary interface, including component overhang.
Manufacturing limitations
Very narrow slots need a smaller mill bit, which is slower to cut and more prone to breakage; very long, thin slots weaken the board mechanically and complicate panelization and depanelization.
Routing constraints
No trace, via, or plane may cross a slot without breaking the isolation it creates. Components spanning a slot must have their own certified internal creepage/clearance (this is exactly what an optocoupler package provides).
Slot geometries
Milling tolerances
| Parameter | Typical fabricator capability | Design margin to add |
|---|---|---|
| Minimum slot width | 0.5–0.8 mm (standard); 0.3–0.4 mm (advanced shops) | Design 20–30% wider than the calculated minimum |
| Position tolerance | ±0.1–0.15 mm typical | Subtract this from your as-designed creepage margin, never add it |
| Slot-to-board-edge spacing | ≥ 0.5–1.0 mm to avoid breakout | Keep slots away from panel rails and tooling holes |
| Aspect ratio (length : width) | Beyond ~20:1 the web becomes fragile | Use multiple shorter slots instead of one very long, thin slot |
Before & after
All spacing comes from raw copper-to-copper distance — any contamination on that flat 8 mm gap shortens the effective creepage directly.
The milled slot roughly triples the surface path in the same board footprint — same real estate, far more creepage margin.
The barrier is not just "the gap" — it's a designed zone with its own rules: no copper crossing it, a documented keep-out width, visible marking so assembly and rework never bridge it, and often a physical or mechanical reinforcement where board-level spacing alone cannot meet the safety margin.
Physical separation
The actual creepage/clearance-compliant gap between primary and secondary copper, sized per Sections 2–3.
Copper keep-out zones
A defined no-copper band on every layer (not just top/bottom) — internal planes are a common place for this rule to be forgotten.
Silkscreen markings
A printed "DO NOT ROUTE" or hazard-voltage marking over the barrier warns rework technicians and assembly QC before a bodge wire ever bridges it.
Mechanical barriers
Slots, plastic barrier ribs, or potting can supplement copper spacing when the two sides must sit closer than bare-board creepage allows.
Test points
Safety test points (Hi-Pot, insulation resistance) need clear primary- and secondary-side access without ever touching a probe across the gap by accident.
Component placement
Nothing with exposed conductive bodies (heatsinks, shields, connector shells) should overhang the barrier, even if its pins don't.
Interactive isolation boundary diagram
An optocoupler's entire job is to break the conductive path between two grounds. Connecting those grounds anywhere else on the board — a stray via, a "just in case" 0Ω resistor, an unintentional plane overlap — re-creates the exact conductive loop the part was placed to remove, and defeats the isolation as completely as leaving the optocoupler off the board entirely.
Primary Ground
Reference for the mains-side / input circuitry. Often noisy (switching, rectified ripple) and not user-accessible.
Secondary Ground
Reference for the isolated / user-accessible or control-side circuitry. Must stay galvanically separate from primary ground.
Chassis Ground
The metal enclosure or frame, often earthed for safety; may be capacitively coupled to one side only via a Y-capacitor, never solidly bonded to both.
Earth Ground
Protective earth conductor from the mains supply — a safety reference, not a signal reference; keep signal return current off it.
Functional Ground
A local reference used for signal integrity within one side only (e.g. an analog vs digital split within the secondary side) — still fully contained on its side of the barrier.
Shared ground vs. isolated grounds
A via, mounting screw, or stray copper reconnects primary and secondary ground, forming a loop that both defeats isolation and injects ground-loop noise into both sides.
Each side has its own single-point ground reference; the only connection between them is the light signal inside the optocoupler.
Animated return current paths
Every signal current has to return to its source — there is no such thing as current that only flows one way. At DC, the return current takes the path of least resistance. At the switching frequencies an optocoupler's LED and output transistor operate at, it takes the path of least impedance, which above a few hundred kHz is almost always the plane directly beneath the signal trace — not the shortest resistive path, and not necessarily where the DC designer expects it.
Current loops
Signal-out + return-current-back forms a physical loop; the loop's enclosed area sets how effectively it radiates and how much it picks up.
Loop inductance
Larger loop area means more loop inductance, which means more ringing, slower edges, and a larger di/dt-driven voltage spike at every transition.
EMI generation
A loop is effectively a small transmitting antenna; radiated emissions scale with loop area × loop current × frequency squared, in simplified terms.
Common-mode current
Current that flows the "wrong" way relative to its intended return — often through chassis or cabling — is the dominant driver of radiated EMI failures.
Differential-mode current
The intended signal/return pair. Well-behaved differential current in a tight loop radiates far less than the common-mode current that escapes it.
Good vs. poor return path
Radiated emissions
Energy leaving the board as an electromagnetic wave, mostly from current loops and long traces acting as unintentional antennas.
Conducted emissions
Noise leaving via cables and power connections rather than through the air — often the same source, a different exit path.
Capacitive coupling
An electric field from a high-dV/dt node induces current on a nearby conductor through the parasitic capacitance between them.
Inductive coupling
A changing magnetic field from a high-dI/dt loop induces a voltage in a nearby loop through mutual inductance.
Crosstalk
The general term for unwanted coupling (capacitive and/or inductive) between two nearby traces or loops on the same board.
Electric field coupling
Dominant when source impedance is high and voltage is the aggressor (e.g. a fast-edge gate-drive trace).
Magnetic field coupling
Dominant when source impedance is low and current is the aggressor (e.g. a high-current switching loop).
Field-line animation: capacitive vs. inductive coupling
Six habits of EMI-aware routing
1. Minimize loop area
Route signal and return current as close together as possible — directly above/below beats routed-far-apart every time.
2. Short traces
Shorter traces are shorter antennas and accumulate less loop area per unit length of routing.
3. Proper grounding
Solid, unsplit reference planes under high-frequency signals; single-point connections between separate ground domains.
4. Shielding
Grounded copper pour or a metal can around a sensitive or noisy node intercepts field lines before they couple elsewhere.
5. Filtering
Ferrite beads and RC/LC filters on cables and I/O suppress conducted noise before it reaches a radiating length of wire.
6. Decoupling
Local bypass capacitors placed tight to the supply pins keep high-frequency switching current in a tiny local loop instead of pulling it across the board.
An optocoupler dissipates power in two places: the LED (forward current × forward voltage) and the output transistor/detector (collector current × VCE(sat), or gate-driver output stage losses). Both raise junction temperature, and junction temperature is what actually drives LED light-output aging and CTR degradation over the product's mission profile — not the ambient temperature alone.
Copper spreading
A generous copper pour under and around the package (respecting the isolation keep-out) spreads heat laterally before it has to escape through the package's thermal resistance.
Thermal vias
An array of vias under a thermal pad conducts heat to an internal or bottom-layer copper spreader — only usable on the side of the barrier that owns that pad, never crossing it.
Thermal relief
The flip side: pads on a solid plane need thermal relief spokes for solderability, which locally reduces heat spreading right where a hot pin needs it most — a real trade-off, not a free lunch.
Package thermal resistance (θJA)
Datasheet junction-to-ambient resistance assuming a specific board (often a JEDEC test board) — real θJA on your board depends heavily on copper area.
Interactive junction temperature & heat map
| Device class | Typical speed | Layout priority |
|---|---|---|
| High-speed logic optocoupler (e.g. 6N137-class) | 1–10 Mbps | Controlled-impedance single-ended trace, solid ground reference each side, short stub to the receiver input |
| Gate-driver optocoupler (e.g. HCPL-3120-class) | Switching edge in tens of ns, amp-level output | Short, wide output trace to the gate; kept clear of the CMTI-stressed barrier; low-inductance decoupling at the driver supply |
| Digital isolator (capacitive/magnetic, for comparison) | 10–150+ Mbps | Often differential (two pins per channel); needs matched trace length and a continuous reference plane on both sides of its own barrier |
Controlled impedance
Trace width/spacing/dielectric height set to hit 50Ω (single-ended) or 90–100Ω (differential) so a fast edge doesn't reflect off an impedance step.
Trace length matching
Matters most for differential digital-isolator pairs and multi-bit parallel buses — keeps edges arriving together.
Differential routing
Tight, consistent spacing between the pair rejects common-mode noise picked up along the route.
Stub reduction
Any unterminated branch off a high-speed trace reflects energy back onto the line — keep test points and via stubs short or eliminate them.
Ground reference
A fast signal needs an uninterrupted reference plane beneath it for its entire length — crossing a plane split is one of the most common signal-integrity mistakes.
Signal integrity
The combined result of all the above: clean edges, low jitter, and enough eye opening for the receiver to sample reliably.
Eye diagram comparison
| Insulation class | What it protects against | Typical creepage multiple vs. basic* |
|---|---|---|
| Functional | Needed only for the circuit to work; no shock-protection role | 1× (no safety margin implied) |
| Basic | Single level of protection against electric shock | 1× (reference) |
| Supplementary | Added in addition to basic to give double insulation | ≈1× basic (independent layer) |
| Double | Basic + supplementary as two independent systems | Two independent basic-level barriers |
| Reinforced | Single insulation system equivalent to double | ≈1.6× basic spacing (varies by standard/voltage) |
*Illustrative ratio only — exact multiples are voltage- and standard-dependent; always use the applicable standard's table.
Examples by application
Consumer products
IEC 62368-1, basic or double insulation typical; PD2 assumed indoors.
Industrial equipment
IEC 61010, often PD3 due to cabinet dust/condensation; reinforced insulation common at the mains interface.
Medical equipment
IEC 60601-1 adds Means of Patient Protection (MOPP) — typically the largest spacing requirement of any product family at the same working voltage.
EV chargers
IEC 62109-family and regional standards demand reinforced insulation for the 400–800 V DC bus to low-voltage control/communication circuits, often at OVC III.
Mechanical spacing around board features
Connectors
Pin-to-pin and pin-to-shell creepage/clearance must be maintained even with a mating connector inserted and under mechanical tolerance stack-up.
Mounting holes
A metal standoff or screw through a mounting hole is a conductor — treat it like any other conductive part when checking spacing to the isolation barrier.
Heat sinks
Often tied to a device tab that may be at a hazardous potential; spacing to the heatsink (and any user-accessible surface it presents) must be checked, not just spacing to other copper.
Metal enclosures
The enclosure itself is a conductor at chassis/earth potential (or floating) — internal clearance from primary-side copper to the enclosure wall is a distinct spacing check from board-level creepage.
Five recurring layout patterns, shown side by side.
Example 1 — Overall barrier layout
Full calculated creepage/clearance maintained, no copper crosses the barrier keep-out, and signal return current stays tight to its trace.
Copper under the optocoupler body, a ground trace bridging primary and secondary, and spacing tighter than calculated — three independent violations in one footprint.
Example 2 — Isolation slot
Milled slot present, tripling the effective surface path in the same footprint.
Same board width relies entirely on the flat gap — any contamination shortens the real creepage directly, with no design margin to fall back on.
Example 3 — Ground planes
Two independent plane fills with a clean, unbridged gap between them.
Autorouter or copy-paste error left both plane fills overlapping — a direct, low-impedance short across the isolation barrier.
Example 4 — Decoupling
Capacitor placed directly at the pin with a short, wide connection — minimal loop inductance.
The same capacitor value routed far away adds enough loop inductance to make the decoupling nearly ineffective at the frequencies that matter.
Example 5 — High-speed routing
Continuous reference plane, minimal stub length, controlled impedance maintained end to end.
The trace crosses a split reference and feeds an unterminated stub — both are classic causes of reflection-driven eye closure.
Drag inside the viewer to rotate the board. Use the layer and overlay toggles to build up the picture — from bare copper to the full isolation, thermal, and field-line picture — and the exploded view to see how the layers stack.
OPTO
Layers
Overlays
| Consideration | Typical guidance |
|---|---|
| PCB fabrication tolerances | ±0.1–0.15 mm on external features is common; subtract this from your as-designed margin, don't add it as free spacing. |
| Minimum slot width | 0.5–0.8 mm standard capability; 0.3–0.4 mm at advanced shops for an added cost/lead-time premium. |
| Copper-to-edge spacing | ≥ 0.3–0.5 mm from routed board edge to avoid exposed copper and delamination risk. |
| Solder mask | Mask dams as thin as 0.1 mm are possible but fragile; mask alone is not a certified insulation layer for spacing credit unless specifically qualified. |
| Silkscreen | Minimum text height ~0.8–1 mm for legibility after reflow; keep hazard markings off pads and vias. |
| Via placement | No via directly under a package body unless via-in-pad is qualified for that footprint; never place a via inside the barrier keep-out. |
| Conformal coating | Requires a coating keep-out around connectors/test points, and a defined coating thickness if credited toward pollution-degree reduction. |
| Assembly limitations | Reflow profile must suit both the optocoupler's moisture sensitivity level (MSL) and any nearby thermally-sensitive parts. |
| AOI inspection | Automated optical inspection can flag solder bridging near the barrier but not spacing violations baked into the copper design — that's a DRC/DFM check, not an AOI check. |
| DFM guidelines | Design-for-manufacture review should explicitly include creepage/clearance and slot geometry, not just solderability and panelization. |
IPC Class 2 vs. Class 3
| IPC Class 2 (general electronics) | IPC Class 3 (high reliability) | |
|---|---|---|
| Typical use | Consumer, most industrial | Medical, aerospace, life-support, harsh-environment |
| Annular ring / via tolerances | Looser | Tighter, more rejectable defect categories |
| Inspection rigor | Standard AOI/visual | More extensive, often 100% inspection with tighter accept/reject criteria |
| Practical effect on this module | Standard creepage/clearance margins are usually sufficient | Often paired with reinforced insulation and extra design margin beyond the bare standard minimum |
| Standard | PCB-relevant requirement |
|---|---|
| IEC 60664-1 | The base creepage/clearance methodology (PD, material group, CTI, altitude) that every other standard below references. |
| IEC 61010 | Test/measurement/lab equipment: applies IEC 60664-1 spacing plus construction requirements for accessible parts and working voltage limits. |
| IEC 60601-1 | Medical: adds Means of Patient/Operator Protection (MOPP/MOOP) spacing on top of basic creepage/clearance, generally the largest margins of the group. |
| IEC 62368-1 | Audio/video/IT equipment (hazard-based standard): spacing requirements tied to energy-source classification rather than a fixed voltage table alone. |
| UL 840 | US-harmonized creepage/clearance standard, closely aligned with IEC 60664-1's structure and tables. |
| IPC-2221 | Generic PCB design standard: conductor spacing tables, often cited alongside (not instead of) the safety-agency creepage/clearance requirement. |
| IPC-9592 | Power conversion equipment performance/design requirements, including layout guidance relevant to isolated power supplies. |
| IEC 62109 | Safety of power converters for photovoltaic systems: applies reinforced-insulation-grade spacing to the PV-to-grid and PV-to-communication interfaces. |
Design checklist — regulatory readiness
Eight full design walk-throughs. Each covers isolation boundary, stack-up, creepage and clearance analysis, return-current path, EMI, thermal, safety, and a design checklist — the same review sequence a certification-focused design review should follow. Figures are representative teaching values; always run the actual numbers for your specific board and component certificates.
Isolation Slot Optimizer
PCB Safety Checker
EMI Layout Advisor
Illustrated with the diagrams and animations built earlier in this module rather than field-failure photography — the root causes below are the same ones that show up in real returned-unit failure analysis.
Copper pours under the isolation barrier
Root cause: autorouter or copy-paste fill left a ground/power pour running under the optocoupler footprint, silently reducing effective creepage to a thin sliver of solder mask. See Section 1's demonstration and Section 5's keep-out overlay.
Insufficient creepage
Root cause: spacing set from a remembered rule of thumb instead of the actual PD/material-group/voltage lookup in Section 2 — often discovered only at certification review.
Insufficient clearance
Root cause: working-voltage-only spacing without accounting for impulse withstand, overvoltage category, or altitude (Section 3) — passes Hi-Pot in the lab, fails a surge test in the field.
Incorrect slot dimensions
Root cause: slot width designed at the fabricator's advertised minimum with no tolerance margin, resulting in filled or missing slots on some panels (Section 4).
Crossing traces (across the barrier)
Root cause: a rework bodge wire, test point jumper, or auto-router escape route drawn straight across the keep-out zone under time pressure.
Shared grounds
Root cause: a "temporary" 0Ω link left in from bring-up debugging, or a mounting screw that happens to bridge chassis to both ground domains (Section 6).
Long return loops
Root cause: signal routed on one layer with its return current forced around a plane split, ballooning loop area and radiated emissions (Section 7).
Poor decoupling
Root cause: decoupling capacitor value correct but placed far from the pin, or sharing a via with an unrelated net, adding loop inductance that defeats its purpose (Section 8/12).
Thermal hot spots
Root cause: no copper spreading or thermal vias under a package expected to dissipate real power, discovered only when field returns cluster around high-ambient installations (Section 9).
High-speed routing errors
Root cause: an "it's just a digital signal" assumption applied to a signal fast enough to need controlled impedance and stub control (Section 10).
Missing safety spacing
Root cause: spacing calculated for the component but not re-checked around connectors, mounting hardware, or the enclosure wall (Section 11).
Incorrect package orientation
Root cause: a symmetric-looking footprint let the part be placed rotated 180°, quietly swapping which side of the barrier each pad's copper actually connects to.
Ignoring altitude corrections
Root cause: clearance calculated at sea level for a product later deployed at altitude (rooftop solar, mountain installations) without reapplying the Section 3 altitude factor.
Ignoring contamination and pollution degree
Root cause: PD2 (clean indoor) assumed by default on a product that actually ships into a dusty, humid, or condensing industrial cabinet (PD3) or outdoor enclosure (PD3/PD4).
Part A — Multiple Choice (25 questions)
Part B — True / False (15 questions)
Part C — PCB Layout Review Exercises (10)
Part D — Creepage & Clearance Calculations (10)
Part E — Drag-and-Drop Matching (5)
Part F — Design Challenge Scenarios (5)
Downloadable Resources
Interactive on-page checklists — check items off as you complete a review, then use your browser's print function to keep a signed-off copy.