Lesson 10/1759%
MODULE 10

Optocoupler Design Examples

Complete, values-included reference designs: MCU input/output isolation, a 24 V PLC input channel with surge protection, TL431 + PC817 SMPS feedback with loop compensation, an IGBT gate-drive stage, mains zero-cross detection, and isolated UART/RS-485 links.

Learning Objectives

After completing this module, you will be able to:

Design isolated MCU interfaces with full component values
Build robust 24 V PLC input channels
Implement and compensate SMPS optocoupler feedback
Design gate-driver stages with proper bypassing and CMTI margin
Implement zero-cross detection and isolated communication links
Where this fits. Everything so far comes together here. Each example follows the same pattern: requirements, schematic, worst-case calculations, BOM, layout notes, common mistakes and verification. The CTR factors (kIF, kT, kage) come from Modules 6 and 9; the families from Module 5; the physics from Module 4. Component values are reference designs for learning: re-check them against your parts’ datasheets and your standards.
Illustrations and animations are original teaching drawings, not to scale. Values marked representative are typical of common parts; always confirm against the current datasheet or standard you design to.

Every example uses the same worst-case method, so you can reuse it for any interface:

Requirements
→
Family & part (Mod. 5, 8)
→
Worst-case CTR / threshold (Mod. 6, 9)
→
Resistors & speed (Mod. 4)
→
Isolation & layout (Mod. 8, 11)
→
Verify (Mod. 13)
Worst case: IF,min from Vdrive,min, VF,max, Rmax  ·  CTREOL = CTRmin·Πk  ·  k = CTREOL·IF,min / IC,needed ≥ 2

Requirements

  • Isolate a 5 V logic signal from a remote domain into a 3.3 V MCU
  • Signal up to 5 kHz; industrial ambient to 70 °C; 10-year life
  • Functional isolation, standard creepage
Schematic: a remote 5 V driver feeds a PC817C LED through 390 ohms; the phototransistor pulls a 4.7 kilohm pull-up to 3.3 V into an MCU GPIO
Figure 1. Isolated logic input. Inverting: LED on gives a logic low.

Step-by-step calculation (worst case)

Calculation
  1. IF,min = (5.0 − 0.4 − 1.4) / 390 Ω ≈ 8.2 mA (driver drop 0.4 V, VF,max 1.4 V). IF,max ≈ (5.25 − 1.0)/390 ≈ 10.9 mA: fine for life.
  2. IC,needed = (3.3 − 0.2)/4.7 kΩ ≈ 0.66 mA.
  3. CTREOL = 200 % (rank C) × 0.9 × 0.8 × 0.5 = 72 %; IC,avail = 8.2 × 0.72 ≈ 5.9 mA → k ≈ 9.
  4. Speed: τ ≈ 1.5 µs + 250 × 10 pF × 4.7 kΩ ≈ 13 µs → tr ≈ 30 µs: fine for 5 kHz. Deep overdrive adds a few µs of storage; acceptable here.

Calculator: LED Resistor + Pull-up Designer

Rounds RLED down to the E24 series, then checks saturation at end of life and estimates edge speed with the Module 4 model.

RLED–
IF range–
IC needed–
IC available at EOL–
Output edge / usable rate–
–

Bill of materials

RefPartValue / ratingWhy
R1Resistor390 Ω, 1 %Sets IF ≈ 8–11 mA
U1PC817C (rank C) or equivalentSMD version for reflowCTR 200–400 %
R2Resistor4.7 kΩPull-up to 3.3 V
C1Capacitor (optional)100 pFGlitch filter, adds ≈ 0.5 µs

Layout notes

Keep the remote-side traces (LED loop) on the remote side of the barrier and the GPIO side on the MCU side; no copper crossing under the part. Pull-up close to the MCU. See Module 11 (PCB Design Guidelines).

Common mistakes

Designing with typical CTR

300 % “typical” hides a 50 % unranked minimum.

Huge pull-up to “save current”

47 kΩ makes edges > 200 µs.

Floating LED drive at reset

A tri-stated remote pin can leave the LED half-on.

Test and verification

  • Measure ton/toff at max temperature
  • Reduce IF to 50 % and confirm the output still saturates (EOL simulation)
  • Check VOL ≤ VIL of the MCU at max IC

Requirements

  • 3.3 V MCU switches a 24 V, 20 mA relay coil on an isolated 24 V supply
  • Relay on/off at ≤ 10 Hz; fail-safe OFF at MCU reset
Schematic: a 3.3 V GPIO drives a PC817 LED through 220 ohms; the phototransistor pulls down the gate of an N-MOSFET that switches a 24 V relay coil with a flyback diode
Figure 2. MCU output to a relay via a phototransistor and a MOSFET. A 24 V gate drive needs a clamp or divider.

Step-by-step calculation (worst case)

Calculation
  1. IF,min = (3.3 − 0.3 − 1.4)/220 Ω ≈ 7.3 mA; check the GPIO current rating (typ. 8–20 mA per pin).
  2. Pull-up 10 kΩ to 24 V → IC,needed = 2.4 mA. Rank B at EOL: 7.3 × 1.3 × 0.36 ≈ 3.4 mA (k ≈ 1.4: marginal). Rank C: ≈ 5.3 mA (k ≈ 2.2).
  3. Gate: 24 V exceeds a typical ±20 V VGS,max. Use a 10 kΩ/10 kΩ divider (12 V gate) or a 15 V zener clamp.
  4. Coil 24 V / 1.2 kΩ = 20 mA; the MOSFET dissipates only I²RDS(on); the flyback diode clamps the turn-off spike.

Bill of materials

RefPartValue / ratingWhy
R1Resistor220 ΩIF ≈ 7–9 mA
U1PC817Crank CMargin at 24 V pull-up
R2/R3Divider10 kΩ / 10 kΩ12 V gate drive
Q1N-MOSFET60 V, logic-level not requiredRelay switch
D11N4148 / 1N4007flybackClamps coil kick

Layout notes

Put the relay coil, MOSFET and flyback diode in a tight loop on the 24 V side; keep the relay’s contacts and their creepage away from the optocoupler area. See Module 11 (PCB Design Guidelines).

Common mistakes

Forgetting the inversion

LED on = relay off in this topology; decide which state is fail-safe.

No flyback diode

Hundreds of volts of inductive kick.

24 V straight onto the gate

Destroys a ±20 V gate.

Test and verification

  • Power-cycle the MCU and confirm the relay stays off during reset
  • Scope VDS at turn-off with the diode fitted
  • Run at max ambient with 50 % IF

Requirements

  • 24 V DC current-sinking input, IEC 61131-2 type 1 or 3 (representative regions: OFF ≤ 5 V; ON 11/15–30 V at 2–15 mA)
  • Reverse-polarity and surge tolerant (IEC 61000-4-5 level per product standard)
  • Low self-heating: 16 inputs per module
Schematic of a 24 V PLC input: reverse diode, TVS, series resistor 3.9 kilohms, 470 ohm shunt across the LED with an anti-parallel diode, PC817 output with a pull-up to 3.3 V into an MCU
Figure 3. The shunt resistor R2 gives a defined turn-on threshold of about 10 V, well away from both the OFF region and the ON minimum.
Animation: input voltage sweeps from 0 to 30 V; the input current and LED current curves are shown against the IEC 61131-2 OFF and ON regions; the LED turns on near 10 V
Animation 1. The input characteristic must stay inside the standard’s regions: no LED current below 5 V, ≥ 2 mA above the ON minimum, ≤ 15 mA at 30 V.

Step-by-step calculation (worst case)

Calculation
  1. Threshold Vth ≈ VD1 + VLED·(R1 + R2)/R2 = 0.7 + 1.05 × 4370/470 ≈ 10.5 V.
  2. At 15 V: Iin ≈ (15 − 0.7 − 1.1)/3.9 kΩ ≈ 3.4 mA (≥ 2 mA); ILED ≈ 3.4 − 1.1/470 ≈ 1.0 mA.
  3. At 30 V: Iin ≈ 7.2 mA (≤ 15 mA); PR1 ≈ 0.2 W → 0.5 W part, pulse-rated for surge.
  4. Output: ILED ≈ 1 mA at the ON minimum. With CTREOL ≈ 70 % at 1 mA (rank C × low-current × temperature × ageing), IC ≈ 0.7 mA; a 22 kΩ pull-up needs 0.14 mA → k ≈ 5.

Calculator: PLC Input Characteristic

Representative IEC 61131-2 regions for 24 V DC sinking inputs — confirm with the current edition. D1 = 0.7 V and VLED = 1.05 V assumed.

Turn-on threshold–
At 5 V (must be OFF)–
At VH,min (must be ON)–
At 30 V (max)–
IC available / needed–
–

Bill of materials

RefPartValue / ratingWhy
D1Diode1N4148 or S1xReverse polarity
TVSSMBJ33A classstand-off ≥ 30 VSurge clamp
R1Resistor3.9 kΩ, 0.5 W, pulse-ratedCurrent limit / threshold
R2Resistor470 ΩThreshold shunt
D21N4148anti-parallelLED reverse protection
U1PC817C / TLP185rank CIsolation
R3Resistor22 kΩPull-up

Layout notes

Field-side parts (D1, TVS, R1) at the connector; TVS return to the field 0 V with a short trace. Keep 24 V field copper out of the logic area; channel-to-channel spacing per the module’s isolation concept. See Module 11 (PCB Design Guidelines).

Common mistakes

No threshold shunt

Leakage from 2-wire sensors turns inputs on in the OFF region.

0.125 W resistor

Overheats with 16 channels at 30 V.

Relying on the TVS alone

The series resistor must survive surge current too.

Test and verification

  • Sweep 0–30 V and plot Iin and the logic state (compare with Animation 1)
  • Apply reverse 30 V and surge per the product standard
  • Thermal image with all inputs on at 30 V

Requirements

  • 12 V / 2 A flyback, current-mode controller with a 5 V-referenced FB pin (RPU internal or external 4.7 kΩ)
  • Crossover ≈ 1–2 kHz; phase margin ≥ 45° over CTR spread and temperature
  • Reinforced isolation mains → SELV (IEC 62368-1)
Schematic of TL431 and PC817 flyback feedback: on the secondary side V_OUT feeds R_LED to the optocoupler LED, whose cathode goes to the TL431 cathode; a divider R_UP and R_LOW sets the reference; R_Z and C_Z compensate; on the primary side the phototransistor pulls down the controller FB node with pull-up R_PU and C_FB
Figure 4. The classic TL431 + optocoupler loop with a “fast lane” RLED from VOUT.

Step-by-step calculation (worst case)

Calculation
  1. VOUT = 2.495 × (1 + 10k/2.61k) ≈ 12.05 V.
  2. TL431 bias: RBIAS = VF/1 mA ≈ 1.2 kΩ → use 1 kΩ (keeps ≥ 1 mA in the TL431 even when the LED is off).
  3. LED headroom: max LED current = (12 − 1.2 − 2.5 VKA,min)/2.2 kΩ − 1.2 mA (bias) ≈ 2.6 mA. FB pull-down needs ≈ 5 V/4.7 kΩ ≈ 1.1 mA; at CTREOL 50 % that is 2.1 mA of LED current: OK.
  4. Compensator: G = CTR·RPU/RLED = 1.0 × 4.7/2.2 ≈ 2.1 (6.6 dB); mid-band ×(1 + RZ/RUP) = 4.3 (12.6 dB); zero at 1/(2π·10 nF·20 kΩ) ≈ 800 Hz.
  5. With a plant of 6 dB and a 200 Hz pole, crossover ≈ 1.7 kHz and PM ≈ 67° at CTR 100 %. At CTR 300 %, gain rises ≈ 9.5 dB: re-check PM (interactive below).

Interactive: Feedback-Loop Designer (Bode)

Simplified model: T(s) = Gplant(s)·H(s), plant = single pole plus an ESR zero at 20 kHz; H(s) = (CTR·RPU/RLED)·(1 + s·CZ(RUP + RZ))/(s·CZRUP)·1/(1 + s/ωopto). Sweep CTR between its EOL minimum and maximum.

Crossover fc–
Phase margin–
Compensator zero–
Mid-band compensator gain–
–

Bill of materials

RefPartValue / ratingWhy
U1TL431 (0.5 % or 1 %)VKA ≥ 2.5 VReference + error amp
U2PC817 (VDE option), narrow rankreinforced packageIsolated error path
RLEDResistor2.2 kΩFast-lane gain
RBIASResistor1 kΩTL431 min. current
RUP/RLOWResistors 0.1–1 %10 kΩ / 2.61 kΩSets VOUT
RZ, CZR, C0G/X7R10 kΩ, 10 nFIntegrator + zero
CFBCapacitor≤ 1 nFNoise filter (adds a pole)

Layout notes

The optocoupler straddles the transformer’s isolation slot; keep primary FB traces short and away from the switch node (dV/dt couples into the high-impedance FB node); keep the TL431 divider away from secondary rectifier noise. See Module 11 (PCB Design Guidelines).

Common mistakes

Compensating at typical CTR

At max CTR the loop gain is 3× higher: oscillation in some units.

Missing RBIAS

TL431 drops below 1 mA at light load: regulation fails.

Big CFB

Adds a low pole on top of the opto pole: phase margin collapses.

Test and verification

  • Measure the loop with an injection transformer (e.g. 20–50 Ω injection resistor in the divider) at min/max load and line
  • Repeat with a high- and a low-CTR sample, and at hot/cold
  • Load-step test: overshoot and ringing consistent with the measured PM

Requirements

  • Drive a 1200 V, 100 A IGBT module (QG ≈ 600 nC) at 10 kHz from an MCU PWM
  • Reinforced isolation to the control side; DC bus 800 V; switching dV/dt up to ≈ 10 kV/µs (IGBT) or 50+ kV/µs (SiC)
  • Short-circuit protection within ≈ 10 µs
Schematic: MCU PWM sinks the LED current of an HCPL-3120 or ACPL-332J; the output side runs from an isolated plus 15 V and minus 8 V supply with bypass capacitors and drives an IGBT gate through separate turn-on and turn-off resistors
Figure 5. Gate-drive stage with bipolar supply and split gate resistors.
Animation of gate-emitter voltage at turn-on for gate resistors of 2.2, 10 and 33 ohms, showing longer Miller plateaus with larger resistance
Animation 2. The gate resistor sets how fast the gate charges through the Miller plateau, and so the collector dV/dt, EMI and switching loss.

Step-by-step calculation (worst case)

Calculation
  1. LED: IF = (5 − 1.8 − 0.3)/270 Ω ≈ 10.7 mA (within a typical 7–16 mA recommended range).
  2. Peak gate current ≈ (15 − (−8))/(10 + 3 + 2) Ω ≈ 1.5 A ≤ 2.5 A rating.
  3. Gate power = 600 nC × 23 V × 10 kHz ≈ 0.14 W; average supply current = QG·f = 6 mA: size the isolated DC-DC with margin.
  4. CMTI: IGBT at 10 kV/µs → a ≥ 25–35 kV/µs driver gives 2.5×+ margin. For SiC at 50–100 kV/µs choose a driver rated ≥ 100–150 kV/µs.
  5. DESAT: blanking time sized so detection completes within the module’s short-circuit withstand time (≈ 10 µs class).

Calculator: Gate Resistor and Peak Current

Resistances in Ω, QG in nC, f in kHz. Driver output resistance is representative; use the datasheet’s IOH/IOL curves for your part.

Peak gate current–
Gate drive power QG·ΔV·f–
Average supply current–
Dissipation in RG (per edge type)–
Rough switching (plateau) time–
–

Bill of materials

RefPartValue / ratingWhy
U1HCPL-3120 / ACPL-332J classreinforced, wide SODriver + isolation
RLEDResistor270 ΩIF ≈ 10 mA
RG,on/RG,offPulse-rated resistors10 Ω / 4.7 ΩEdge-rate control
C1, C2Ceramic + bulk100 nF + 10 µF on each railSupply the gate-current peaks
RGEResistor10 kΩ gate–emitterHolds off when unpowered
PS1Isolated DC-DC+15/−8 V, ≥ 1 W, reinforcedFloating supply

Layout notes

Minimise the gate loop area (driver → RG → gate → emitter → driver); use a Kelvin emitter connection; place 100 nF directly at the driver pins; keep the switch node away from the driver’s input side; respect the package creepage on the PCB with a slot if needed. See Module 11 (PCB Design Guidelines).

Common mistakes

No negative rail and no Miller clamp

dV/dt of the other switch turns this one on through CGC: shoot-through.

Bypass caps far away

Supply droop during the 1.5 A peak trips UVLO.

CMTI chosen for IGBT, used with SiC

False pulses at 50+ kV/µs.

Test and verification

  • Double-pulse test: VGE, VCE, IC at max bus and current
  • Short-circuit test with DESAT, verify soft turn-off
  • CMTI check: look for glitches on the fault line during switching

Requirements

  • Detect each zero crossing of 230 V / 50 Hz for TRIAC phase control or power metering
  • Timing uncertainty < ±100 µs after calibration; reinforced isolation to the MCU
Schematic: mains line and neutral through two 47 kilohm resistors into the anti-parallel LEDs of an H11AA1; the phototransistor pulls up to 3.3 V into an MCU capture input
Figure 6. Zero-cross detector. The pulse is centred on the true zero crossing.

Step-by-step calculation (worst case)

Calculation
  1. LED peak current ≈ 325 V / 94 kΩ ≈ 3.5 mA; average (rectified) ≈ 2.2 mA.
  2. Each resistor: 115 Vrms → P ≈ 0.28 W; choose 0.5–1 W, voltage-rated ≥ its share of the surge (or 3 in series).
  3. Pulse width: output high while |Vline| < ≈ 30–50 V (depends on CTR, pull-up and threshold) → ≈ 2 × asin(40/325)/(2π·50) ≈ 0.8 ms.
  4. Timing: use the pulse centre (average of rising and falling edges). That cancels the symmetric widening and makes the result nearly independent of CTR.

Bill of materials

RefPartValue / ratingWhy
R1, R2Resistors47 kΩ, 0.5–1 W, high-voltage ratedCurrent limit, voltage sharing
U1H11AA1 (or AC-input SMD)reinforced option if requiredBidirectional input
R3Resistor22 kΩPull-up
(opt.) CCapacitor1–10 nFFilter mains noise

Layout notes

Mains-side resistors need creepage/clearance between them and to everything else (they carry line voltage). Keep the mains traces on the far side of the slot/barrier, with the resistors oriented along the high-voltage path. See Module 11 (PCB Design Guidelines).

Common mistakes

One small resistor

A 0805 resistor sees 325 V peak and overheats.

Timing from one edge

The edge moves with CTR and temperature.

Ignoring standby power

0.56 W forever can break an energy-efficiency budget.

Test and verification

  • Scope the output against the mains (through a differential probe) and measure the centre error
  • Hot/cold test of pulse width
  • Surge test per the product standard

Requirements

  • UART at 115.2 kbit/s (upgradeable to 1 Mbit/s) between a controller and a field device
  • RS-485 variant: DI, RO, DE isolated, bus side powered by an isolated 5 V supply
  • CMTI ≥ 2× the expected ground-shift dV/dt
Block diagram: MCU TX, RX and DE through three 6N137 couplers to an RS-485 transceiver on the isolated side with a 120 ohm termination and an isolated 5 V DC-DC supply
Figure 7. Isolated RS-485: three logic channels plus isolated power. For plain UART only TX and RX are needed.

Step-by-step calculation (worst case)

Calculation
  1. LED: IF = (3.3 − 0.3 − 1.75)/120 Ω ≈ 10 mA (inside the 6.5–15 mA recommended range).
  2. Pull-up 1 kΩ to 5 V: IOL ≈ 4.4 mA; tr ≈ 2.2 × 1 kΩ × 15 pF ≈ 33 ns.
  3. At 1 Mbit/s: bit = 1000 ns; PWD 35 ns + 33 ns edge ≈ 7 %: comfortable. At 115.2 kbit/s it is < 1 %.
  4. RS-485: DE must enable the driver before the first start bit; the coupler delay (≈ 75 ns) is negligible at these rates.

Calculator: UART Baud-Rate Checker

Estimates edge time from the pull-up and load (open-collector) or a fixed ~10 ns (totem-pole), adds the part’s PWD, and compares with the bit time.

Bit time–
Output rise time–
PWD–
Timing distortion (PWD + edge)–
Output sink current–
–

Bill of materials

RefPartValue / ratingWhy
U1–U36N137 class10 MBd, 0.1 µF eachTX/DI, RO, DE
RResistors120 Ω (LED), 1 kΩ (pull-up)IF and edges
U4RS-485 transceiverfail-safe receiverBus interface
PS1Isolated DC-DC5 V, reinforced if neededBus-side power
RTTermination120 ΩAt bus ends only

Layout notes

Bypass each 6N137 with 0.1 µF at the pins; keep bus-side ground (and its large copper) away from the logic side; route the isolation gap straight under all couplers and the DC-DC. See Module 11 (PCB Design Guidelines).

Common mistakes

Pull-up too small

Exceeds IOL and raises VOL.

Floating enable pin

Noise gates the output.

Forgetting isolated power

The bus side needs its own supply.

Test and verification

  • Eye/timing measurement at the maximum baud rate
  • Common-mode transient test between grounds
  • Bus fault tests (short, open, polarity)
One method, every interface

Worst-case IF, CTREOL, overdrive k ≥ 2, speed, isolation, layout, verification.

MCU I/O

Size RLED with VF,max and driver drop; mind the inversion and fail-safe state.

PLC inputs

A shunt resistor sets a clean threshold; watch resistor power and surge.

Feedback loops

CTR spread changes loop gain: design PM at CTRmax, regulation at CTRmin.

Gate drives

Bipolar supply, split RG, local bypass, CMTI margin, DESAT.

Zero-cross

Resistors carry mains power; time from the pulse centre.

Serial links

PWD + edge ≤ 10–20 % of a bit; bypass and pull-up per datasheet.

Verify at the corners

Hot, cold, low-CTR samples, 50 % IF as an EOL simulation.

Design checklist

Tick items as you review a design. Your ticks are saved in this browser only; use your browser’s print function for a sign-off copy.

Four parts: multiple choice, true/false, a matching exercise and engineering scenarios. Score 80 % on the multiple choice to pass the module.

Part A — Multiple Choice

Question 1 of 10  •  Score: 0/10

Part B — True or False

Score: 0/8

Part C — Match the Term to Its Meaning

Drag each term onto its definition, or click a term and then click a definition.

Placed: 0/6

Part D — Engineering Scenarios

Scenario 1 — Relay chatters at power-up
In Example 2 the relay briefly energises every time the MCU resets. Why, and how do you fix it?
Analysis. During reset the GPIO is high-impedance: the LED is off, the phototransistor is off, and the 10 kΩ pull-up turns the MOSFET on. The topology makes “LED off” = relay on. Fix: invert the output stage (phototransistor drives the MOSFET gate high through a pull-down arrangement) so LED off = relay off, or add a pull-down on the MCU side that keeps the LED on during reset (less clean). Choose the fail-safe state deliberately.
Scenario 2 — Input that turns on with nothing connected
A PLC input without R2 (no LED shunt) reads ON when connected to a 2-wire proximity sensor that leaks 1.5 mA in its off state. Explain using Example 3.
Analysis. Without the shunt, 1.5 mA flows entirely through the LED. At CTR ≈ 100 % that is 1.5 mA of collector current, easily enough to pull a 22 kΩ pull-up low. The standard allows off-state currents up to 1.5 mA (type 3). Fix: add R2 so that off-state current flows through the shunt (1.5 mA × 470 Ω ≈ 0.7 V < VF): the LED stays dark until the input exceeds the threshold.
Scenario 3 — Oscillation with a new CTR rank
A flyback designed with rank A (80–160 %) is changed to rank D (300–600 %) for supply reasons. Some units now oscillate. Explain and fix.
Analysis. Loop gain scales with CTR: rank D can be up to 600/160 ≈ 3.75× (11.5 dB) higher, pushing the crossover up towards the opto pole and reducing phase margin. Fix: scale RPU/RLED down by ≈ the CTR ratio, re-tune RZ/CZ, and re-measure the loop at both CTR extremes. Lock the rank in the BOM.

Additional Resources

Reference material

Vendor application notes: TL431 + optocoupler loop design, PLC input design with optocouplers, gate-driver optocoupler application guides, 6N137 application circuits, AC-input coupler zero-cross notes.

Standards

IEC 61131-2 (PLC I/O) • IEC 62368-1 (ICT/AV supplies) • IEC 61800-5-1 (drives) • IEC 61000-4-x (immunity tests).

Keep learning

Module 11 lays these circuits out; Module 13 verifies them; Module 17 has LTspice labs for several of these designs.