Debugging Workflow & PCB Design
Every case study in Module 07 was solved with the same structured approach: narrow by frequency, isolate DM vs. CM, then fix the physical root cause. This module formalizes that decision tree and covers the PCB layout techniques that prevent most conducted-emission problems before they ever reach the lab.
Click through the tree below the way you would on the bench: start with the failing frequency, and let it point you toward differential-mode or common-mode causes.
Good and bad layout side by side for the four techniques that matter most for conducted (and radiated) emissions.
| Technique | Bad Practice | Good Practice |
|---|---|---|
| Switching loop | Input cap far from the switch node, sprawling hot loop | Input cap immediately adjacent to the switch node, minimal loop area |
| Ground | Split or slotted ground plane under switching traces | Continuous, unbroken ground plane beneath all high-current paths |
| Return path | Return current forced to detour around a slot or gap | Return current follows directly beneath its forward trace |
| Filter placement | Filter placed after noise has already spread across the board | Filter placed immediately at the connector, before noise can spread |
| Via stitching | No stitching vias between ground/power planes | Dense stitching vias, especially near plane edges and connectors |
Module 8 Quiz
Select the best answer for each question. Instant feedback is provided after each response.