Lesson 9/1090%
MODULE 09

Failure Mechanisms, Design & Troubleshooting

Nearly every RE failure traces back to one of a small set of root causes on the PCB or cable. This module pairs each common failure mechanism with an animated before/after diagram of the design fix that addresses it, then lays out a systematic, animated troubleshooting methodology for a board that has already failed — backed by real-style spectrum graphs and the actual near-field debug equipment used on the bench.

Every entry on the left is a root cause seen repeatedly in pre-compliance RE failures; the entry on the right is the design technique that most directly addresses it. The animated diagrams further down physically show why each fix works, not just that it works.

Poor PCB stack-up
→
Ensure proper PCB layer stack-up
Large current loops
→
Minimize loop areas
Inadequate decoupling
→
Place decoupling capacitors close to IC power pins
Long high-speed traces
→
Maintain controlled impedance traces
Split ground planes
→
Use continuous ground planes
Floating copper regions
→
Avoid routing high-speed signals across ground splits
Unshielded cables
→
Shield noisy sections of the design
High clock edge rates
→
Reduce clock edge rates where possible
Common-mode currents on cables
→
Filter cable interfaces with common-mode chokes or ferrites
Poor enclosure shielding
→
Terminate high-speed interfaces correctly
These pairings are not one-to-one in practice — a single failure like "unshielded cables" is often fixed by a combination of cable shielding, common-mode chokes, and improved cable grounding together. Treat the table above as the starting point for diagnosis, not an exhaustive checklist.

Interactive: Typical Emission Reduction by Fix

Approximate real-world dB reduction seen at the offending frequency after applying each fix in isolation on a typical digital board. Actual results vary by board, but the relative ranking is consistent across designs — loop area and ground continuity fixes tend to yield the largest single gains.

Radiated field strength from a current loop scales with the loop's enclosed area. A sprawling trace routed far from its return path (large loop) radiates far more than the same signal routed directly above a solid ground plane (small, tight loop) — even though both carry the identical current.

Animated: Bad Layout vs. Good Layout, Same Signal

Every digital IC draws current in short, sharp pulses as its internal gates switch. Without a decoupling capacitor placed right at the power pin, that pulse has to travel all the way back to the board's bulk supply and back — a large loop that radiates strongly. A capacitor placed within a few millimeters of the pin supplies that current locally instead, collapsing the loop to almost nothing. A proper 4-layer stack-up (signal / ground / power / signal) gives every trace a solid, adjacent return plane so this local decoupling actually works.

Animated: IC Switching Current Path, With and Without Local Decoupling

Animated: 4-Layer PCB Stack-up

Each signal layer sits directly adjacent to a solid reference plane, giving every trace a tightly coupled, low-impedance return path immediately beneath it.

When a high-speed signal's return current reaches a slot or split in the ground plane beneath it, it can't continue in a straight line back to the source. It is forced to detour around the slot — creating exactly the large, uncontrolled current loop Section 2 warned about, and turning the slot edges into an unintentional slot antenna.

Animated: Return Current Detouring Around a Ground Split

An unshielded cable with even a small common-mode current riding on it can radiate more than the entire PCB it's attached to, because the cable is often physically much longer than the internal loop — approaching a resonant antenna length at the frequencies of interest. A ferrite common-mode choke adds high impedance specifically to that common-mode current (while leaving the wanted differential signal untouched), and a shield tied to chassis ground at both ends gives the common-mode current a much shorter path back than the cable itself.

Animated: Cable Radiation, Unfiltered vs. Ferrite + Shield

Troubleshooting Methodology

  1. Identify the failing frequency from the compliance scan.
  2. Correlate the frequency to potential clock sources or harmonics.
  3. Use near-field probes to localize the emission source on the board.
  4. Evaluate PCB layout, return paths, and cable routing at that location.
  5. Apply temporary mitigation (ferrites, shielding, filtering) to isolate the cause.
  6. Validate improvements through iterative pre-compliance testing.

Animated: Near-Field Probe Scanning for the Hotspot

The probe sweeps across the board while the live reading spikes directly over the clock driver — exactly how Step 3 physically pinpoints a source once the failing frequency and likely clock harmonic are already known.

This same six-step methodology is applied to the real case study you'll see in Module 10 — a networking board failing at 300 MHz, traced back to a clock harmonic and a broken return path beneath the routing.

A realistic EMI-receiver-style trace showing the same board before and after applying the Section 2–5 fixes together. Toggle between the two traces to see exactly how much margin was recovered at the failing harmonic against the CISPR Class B limit line.

Bench-level debug uses a different, cheaper equipment set than the chamber itself — the goal here is localizing and iterating quickly, not producing a compliance-grade absolute measurement.

Near-Field Probe Set
Spectrum Analyzer
Current Probe
Ferrite Clamp Kit
Oscilloscope
Copper Shielding Tape
KNOWLEDGE CHECK

Module 9 Quiz

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