EMI/EMC Academy ~35 min Interactive

PCB & Circuit-Level Hardening

Stop the transient at the board: filtering, TVS/varistors, series impedance, decoupling, robust reset and clocks, and disciplined ground layout.

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The first defense is to slow and divert the transient at entry: a small series resistor/ferrite plus a capacitor to a solid ground forms an RC/LC low-pass that robs the nanosecond edge of its high-frequency content. On reset and other critical control lines, a modest RC filter dramatically raises EFT immunity.

Place the filter and its ground return with minimal loop area — a filter with a long ground lead is defeated by its own inductance at burst frequencies.

At exposed I/O, add fast TVS diodes (or MOVs on power) to clamp the transient to a safe level and shunt the current to chassis/ground. Keep the clamp loop tiny and the ground connection low-inductance, or the clamp voltage overshoots. Stage protection: a coarse device at the connector, a fast TVS near the IC.

Decoupling & PDN. Strong local decoupling stiffens the rail so a burst-induced dip doesn't reset the MCU. Short, wide via connections keep it effective at burst frequencies.

Reset & clocks. Filter the reset input, use a supervisor with glitch immunity, and guard oscillator lines — the usual EFT casualties.

Give the common-mode current a short, low-impedance path to chassis that bypasses sensitive circuitry — an I/O ground-stitching row and a chassis-bond near the connector. The goal is to keep the burst current in the "dirty" entry region and out of the board's quiet reference.

Common mistake: routing a noisy I/O ground through the middle of the board to a single star point. At EFT speeds that inductive path lifts the whole reference — bond to chassis right at the connector instead.

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